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Searched refs:PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT (Results 1 – 15 of 15) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h5593 #define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x00000005 macro
H A Dgfx_7_2_sh_mask.h5576 #define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5 macro
H A Dgfx_8_0_sh_mask.h6364 #define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5 macro
H A Dgfx_8_1_sh_mask.h6898 #define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h16898 #define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT macro
H A Dgc_9_1_sh_mask.h18203 #define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT macro
H A Dgc_9_2_1_sh_mask.h18078 #define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT macro
H A Dgc_9_4_3_sh_mask.h20206 #define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT macro
H A Dgc_9_4_2_sh_mask.h10325 #define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT macro
H A Dgc_11_5_0_sh_mask.h18071 #define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT macro
H A Dgc_11_0_0_sh_mask.h22097 #define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT macro
H A Dgc_12_0_0_sh_mask.h30194 #define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT macro
H A Dgc_10_1_0_sh_mask.h24389 #define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT macro
H A Dgc_11_0_3_sh_mask.h24427 #define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT macro
H A Dgc_10_3_0_sh_mask.h22578 #define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT macro