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Searched refs:PA_CL_CLIP_CNTL__UCP_ENA_3_MASK (Results 1 – 15 of 15) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h5588 #define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x00000008L macro
H A Dgfx_7_2_sh_mask.h5571 #define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x8 macro
H A Dgfx_8_0_sh_mask.h6359 #define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x8 macro
H A Dgfx_8_1_sh_mask.h6893 #define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x8 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h16915 #define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK macro
H A Dgc_9_1_sh_mask.h18220 #define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK macro
H A Dgc_9_2_1_sh_mask.h18096 #define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK macro
H A Dgc_9_4_3_sh_mask.h20224 #define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK macro
H A Dgc_9_4_2_sh_mask.h10343 #define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK macro
H A Dgc_11_5_0_sh_mask.h18089 #define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK macro
H A Dgc_11_0_0_sh_mask.h22115 #define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK macro
H A Dgc_12_0_0_sh_mask.h30212 #define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK macro
H A Dgc_10_1_0_sh_mask.h24407 #define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK macro
H A Dgc_11_0_3_sh_mask.h24445 #define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK macro
H A Dgc_10_3_0_sh_mask.h22596 #define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK macro