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Searched refs:PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK (Results 1 – 15 of 15) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h5580 #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x00020000L macro
H A Dgfx_7_2_sh_mask.h5583 #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x20000 macro
H A Dgfx_8_0_sh_mask.h6371 #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x20000 macro
H A Dgfx_8_1_sh_mask.h6905 #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x20000 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h16921 #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK … macro
H A Dgc_9_1_sh_mask.h18226 #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK … macro
H A Dgc_9_2_1_sh_mask.h18102 #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK … macro
H A Dgc_9_4_3_sh_mask.h20230 #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK … macro
H A Dgc_9_4_2_sh_mask.h10349 #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK … macro
H A Dgc_11_5_0_sh_mask.h18095 #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK … macro
H A Dgc_11_0_0_sh_mask.h22121 #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK … macro
H A Dgc_12_0_0_sh_mask.h30218 #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK … macro
H A Dgc_10_1_0_sh_mask.h24413 #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK … macro
H A Dgc_11_0_3_sh_mask.h24451 #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK … macro
H A Dgc_10_3_0_sh_mask.h22602 #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK … macro