Searched refs:NUM_XCC (Results 1 – 16 of 16) sorted by relevance
318 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); in __aqua_vanjaram_calc_xcp_mode()370 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); in __aqua_vanjaram_get_xcc_per_xcp()406 num_xcp = NUM_XCC(adev->gfx.xcc_mask) / num_xcc_xcp; in __aqua_vanjaram_get_xcp_ip_info()464 max_res[AMDGPU_XCP_RES_XCC] = NUM_XCC(adev->gfx.xcc_mask); in aqua_vanjaram_get_xcp_res_info()490 num_xcp = NUM_XCC(adev->gfx.xcc_mask); in aqua_vanjaram_get_xcp_res_info()524 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); in __aqua_vanjaram_get_auto_mode()548 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in __aqua_vanjaram_is_valid_mode()611 switch (NUM_XCC(adev->gfx.xcc_mask)) { in __aqua_vanjaram_update_supported_modes()663 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in aqua_vanjaram_switch_partition_mode()
70 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); in gfxhub_v1_2_setup_vm_pt_regs()439 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); in gfxhub_v1_2_gart_enable()480 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); in gfxhub_v1_2_gart_disable()538 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); in gfxhub_v1_2_set_fault_enable_default()587 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); in gfxhub_v1_2_init()
337 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_set_kiq_pm4_funcs()346 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_init_golden_registers()622 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_mec_init()800 NUM_XCC(adev->gfx.xcc_mask) / in gfx_v9_4_3_switch_compute_partition()1009 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_alloc_ip_dump()1061 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_sw_init()1176 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_sw_fini()1315 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_constants_init()1392 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()1485 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_rlc_stop()[all …]
208 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; in amdgpu_gfx_compute_queue_acquire()1041 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; in amdgpu_gfx_ras_error_func()1369 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in amdgpu_gfx_set_compute_partition()1493 int num_xcc = NUM_XCC(adev->gfx.xcc_mask); in amdgpu_gfx_run_cleaner_shader()
74 #define NUM_XCC(x) hweight16(x) macro
1946 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gmc_v9_0_init_acpi_mem_ranges()2178 NUM_XCC(adev->gfx.xcc_mask)); in gmc_v9_0_sw_init()
361 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; in amdgpu_ras_instance_mask_check()
141 NUM_XCC(node->xcc_mask), in allocate_mqd()549 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { in init_mqd_hiq_v9_4_3()666 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { in init_mqd_v9_4_3()695 NUM_XCC(mm->dev->xcc_mask); in init_mqd_v9_4_3()728 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { in update_mqd_v9_4_3()839 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { in get_wave_state_v9_4_3()
309 * NUM_XCC(pdd->dev->xcc_mask); in kfd_queue_acquire_buffers()356 * NUM_XCC(pdd->dev->xcc_mask); in kfd_queue_release_buffers()441 cu_num = props->simd_count / props->simd_per_cu / NUM_XCC(dev->gpu->xcc_mask); in kfd_queue_ctx_save_restore_size()
80 NUM_XCC(dev->xcc_mask); in allocate_sdma_mqd()109 int inc = cu_inc * NUM_XCC(mm->dev->xcc_mask); in mqd_symmetrically_map_cu_mask()
463 NUM_XCC(dev->gpu->xcc_mask)) : 0); in node_show()531 NUM_XCC(dev->gpu->xcc_mask)); in node_show()1101 buf[7] = (ffs(gpu->xcc_mask) - 1) | (NUM_XCC(gpu->xcc_mask) << 16); in kfd_generate_gpu_id()1672 int num_xcc = NUM_XCC(knode->xcc_mask); in fill_in_l2_l3_pcache()1804 end = start + NUM_XCC(kdev->xcc_mask); in kfd_fill_cache_non_crat_info()
1098 device_info.num_xcc = NUM_XCC(pdd->dev->xcc_mask); in kfd_dbg_trap_device_snapshot()
1116 num_xccs = NUM_XCC(q->device->xcc_mask); in pqm_debugfs_mqds()
872 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1; in kgd2kfd_device_init()
1859 NUM_XCC(dqm->dev->xcc_mask); in start_cpsch()2885 NUM_XCC(dqm->dev->xcc_mask)); in allocate_hiq_sdma_mqd()
317 wave_cnt += (NUM_XCC(dev->xcc_mask) * in kfd_get_cu_occupancy()