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/linux-6.15/drivers/mtd/nand/raw/
H A DKconfig24 Denali NAND controller core.
31 Enable the driver for NAND flash on platforms using a Denali NAND
135 tristate "Atmel AT91 NAND Flash/SmartMedia NAND controller"
175 by the SLC NAND controller.
187 by the MLC NAND controller.
231 external NAND devices.
242 external NAND devices.
278 for NAND Flash using FLCTL.
315 Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached
337 Enables support for NAND flash chips on SoCs containing the EBI2 NAND
[all …]
/linux-6.15/drivers/mtd/nand/raw/brcmnand/
H A DKconfig2 tristate "Broadcom STB NAND controller"
6 Enables the Broadcom NAND controller driver. The controller was
13 tristate "Broadcom BCM63xx NAND controller glue"
16 Enables the BRCMNAND glue driver to register the NAND controller
20 tristate "Broadcom BCMA NAND controller"
29 tristate "Broadcom BCMBCA NAND controller glue"
32 Enables the BRCMNAND glue driver to register the NAND controller
39 Enables the BRCMNAND glue driver to register the NAND controller
43 tristate "Broadcom iProc NAND controller glue"
46 Enables the BRCMNAND controller glue driver to register the NAND
/linux-6.15/Documentation/devicetree/bindings/mtd/
H A Dbrcm,brcmnand.yaml7 title: Broadcom STB NAND Controller
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
27 -- Additional SoC-specific NAND controller properties --
39 register resources within the NAND controller node above.
58 - description: BCMBCA SoC-specific NAND controller
65 - description: iProc SoC-specific NAND controller
70 - description: BCM63168 SoC-specific NAND controller
90 - description: NAND CTLRDY interrupt
103 description: reference to the clock for the NAND controller
142 the flash geometry (particularly the NAND page
[all …]
H A Dnand-controller.yaml7 title: NAND Controller Common Properties
14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This representation should be
35 NAND controller (even if they are not used). As many additional
37 lines. 'reg' entries of the NAND chip subnodes become indexes of
65 /* NAND chip specific properties */
H A Dnand-chip.yaml7 title: NAND Chip Common Properties
16 This file covers the generic description of a NAND chip. It implies that the
17 bus interface should not be taken into account: both raw NAND devices and
18 SPI-NAND devices are concerned by this description.
29 1/ The ECC engine is part of the NAND controller, in this
31 2/ The ECC engine is part of the NAND part (on-die), in this
65 Regions in the NAND chip which are protected using a secure element
H A Dnvidia-tegra20-nand.txt1 NVIDIA Tegra NAND Flash controller
18 Individual NAND chips are children of the NAND controller node. Currently
19 only one NAND chip supported.
25 - nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
27 - nand-ecc-algo: string, algorithm of NAND ECC.
41 Optional child node of NAND chip nodes:
H A Dfsmc-nand.txt2 NAND Interface
13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
27 NAND flash in response to SMWAITn. Zero means 1 cycle,
32 - bank: default NAND bank to use (0-3 are valid, 0 is the default).
47 0xd2000000 0x0010 /* NAND Base DATA */
48 0xd2020000 0x0010 /* NAND Base ADDR */
49 0xd2010000 0x0010>; /* NAND Base CMD */
H A Dti,gpmc-nand.yaml7 title: Texas Instruments GPMC NAND Flash controller.
14 GPMC NAND controller/Flash is represented as a child of the
54 Bus width to the NAND chip
61 GPIO connection to R/B signal from NAND chip
110 /* NAND generic properties */
118 label = "NAND.SPL";
122 label = "NAND.SPL.backup1";
H A Dgpio-control-nand.txt1 GPIO assisted NAND flash
3 The GPIO assisted NAND flash uses a memory mapped interface to
4 read/write the NAND commands and data and GPIO pins for the control
10 resource describes the data bus connected to the NAND flash and all accesses
14 - gpios : Specifies the GPIO pins to control the NAND device. The order of
24 the GPIO's and the NAND flash data bus. If present, then after changing
H A Datmel-nand.txt1 Atmel NAND flash controller bindings
3 The NAND flash controller node should be defined under the EBI bus (see
5 One or several NAND devices can be defined under this NAND controller.
6 The NAND controller might be connected to an ECC engine.
8 * NAND controller bindings:
30 * NAND device/chip bindings:
33 - reg: describes the CS lines assigned to the NAND device. If the NAND device
36 1st entry: the CS line this NAND chip is connected to
42 - rb-gpios: the GPIO(s) used to check the Ready/Busy status of the NAND.
103 * Put generic NAND/MTD properties and
[all …]
H A Dvf610-nfc.txt1 Freescale's NAND flash controller (NFC)
3 This variant of the Freescale NAND flash controller (NFC) can be found on
13 - assigned-clock-rates: The NAND bus timing is derived from this clock
14 rate and should not exceed maximum timing for any NAND memory chip
15 in a board stuffing. Typical NAND memory timings derived from this
24 only handle one NAND chip.
H A Dlpc32xx-mlc.txt1 NXP LPC32xx SoC NAND MLC controller
6 - interrupts: The NAND interrupt specification
7 - gpios: GPIO specification for NAND write protect
10 User Manual 7.5.14 MLC NAND Timing Register (the values here are specified in
H A Dmediatek,nand-ecc-engine.yaml7 title: MediaTek(MTK) SoCs NAND ECC engine
13 MTK NAND ECC engine can cowork with MTK raw NAND and SPI NAND controller.
H A Dingenic,nand.yaml7 title: Ingenic SoCs NAND controller
25 - description: Bank number, offset and size of first attached NAND chip
26 - description: Bank number, offset and size of second attached NAND chip
27 - description: Bank number, offset and size of third attached NAND chip
28 - description: Bank number, offset and size of fourth attached NAND chip
/linux-6.15/drivers/pinctrl/tegra/
H A Dpinctrl-tegra30.c2194 …PINGROUP(gmi_wp_n_pc7, RSVD1, NAND, GMI, GMI_ALT, 0x31c0, N, …
2219 …PINGROUP(gmi_ad0_pg0, RSVD1, NAND, GMI, RSVD4, 0x31f0, N, …
2220 …PINGROUP(gmi_ad1_pg1, RSVD1, NAND, GMI, RSVD4, 0x31f4, N, …
2221 …PINGROUP(gmi_ad2_pg2, RSVD1, NAND, GMI, RSVD4, 0x31f8, N, …
2222 …PINGROUP(gmi_ad3_pg3, RSVD1, NAND, GMI, RSVD4, 0x31fc, N, …
2223 …PINGROUP(gmi_ad4_pg4, RSVD1, NAND, GMI, RSVD4, 0x3200, N, …
2224 …PINGROUP(gmi_ad5_pg5, RSVD1, NAND, GMI, RSVD4, 0x3204, N, …
2225 …PINGROUP(gmi_ad6_pg6, RSVD1, NAND, GMI, RSVD4, 0x3208, N, …
2226 …PINGROUP(gmi_ad7_pg7, RSVD1, NAND, GMI, RSVD4, 0x320c, N, …
2227 …PINGROUP(gmi_ad8_ph0, PWM0, NAND, GMI, RSVD4, 0x3210, N, …
[all …]
/linux-6.15/arch/arm64/boot/dts/ti/
H A Dk3-am62-lp-sk-nand.dtso87 label = "NAND.tiboot3";
91 label = "NAND.tispl";
95 label = "NAND.tiboot3.backup"; /* 2M */
99 label = "NAND.u-boot";
103 label = "NAND.u-boot-env";
107 label = "NAND.u-boot-env.backup";
111 label = "NAND.file-system";
H A Dk3-am642-evm-nand.dtso3 * DT overlay for HSE NAND expansion card on AM642 EVM
113 label = "NAND.tiboot3";
118 label = "NAND.tispl";
123 label = "NAND.tiboot3.backup"; /* 2M */
128 label = "NAND.u-boot";
133 label = "NAND.u-boot-env";
138 label = "NAND.u-boot-env.backup";
143 label = "NAND.file-system";
/linux-6.15/arch/powerpc/boot/dts/fsl/
H A Dp1010rdb-pa.dtsi40 label = "NAND U-Boot Image";
47 label = "NAND DTB Image";
53 label = "NAND Linux Kernel Image";
59 label = "NAND Compressed RFS Image";
65 label = "NAND JFFS2 Root File System";
71 label = "NAND User area";
/linux-6.15/arch/arm64/boot/dts/marvell/
H A Dcn9130-db.dts14 /* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When SPI controller is enabled, NAND should be disabled.
H A Dcn9132-db-B.dts14 /* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
H A Dcn9132-db.dts14 /* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When SPI controller is enabled, NAND should be disabled.
H A Dcn9131-db.dts14 /* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When SPI controller is enabled, NAND should be disabled.
H A Dcn9130-db-B.dts14 /* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
H A Dcn9131-db-B.dts14 /* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
/linux-6.15/Documentation/devicetree/bindings/spi/
H A Dqcom,spi-qpic-snand.yaml7 title: Qualcomm QPIC NAND controller
13 The QCOM QPIC-SPI-NAND flash controller is an extended version of
14 the QCOM QPIC NAND flash controller. It can work both in serial
15 and parallel mode. It supports typical SPI-NAND page cache

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