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Searched refs:MinClock (Results 1 – 25 of 35) sorted by relevance

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/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_smu11_driver_if.h25 uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz) member
/linux-6.15/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu10_driver_if.h51 uint16_t MinClock; /* This is either DCFCLK or SOCCLK (in MHz) */ member
H A Dsmu9_driver_if.h330 uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz) member
/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_clk_mgr.c362 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn316_build_watermark_ranges()
378 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn316_build_watermark_ranges()
391 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in dcn316_build_watermark_ranges()
397 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in dcn316_build_watermark_ranges()
H A Ddcn316_smu.h41 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
/linux-6.15/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu13_driver_if_v13_0_5.h52 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
H A Dsmu13_driver_if_yellow_carp.h50 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
H A Dsmu12_driver_if.h51 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
H A Dsmu13_driver_if_v13_0_4.h51 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
H A Dsmu11_driver_if_vangogh.h50 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
H A Dsmu14_driver_if_v14_0_0.h46 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_smu.h42 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
H A Ddcn315_clk_mgr.c397 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn315_build_watermark_ranges()
413 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn315_build_watermark_ranges()
426 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in dcn315_build_watermark_ranges()
432 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in dcn315_build_watermark_ranges()
/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Dvg_clk_mgr.c400 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in vg_build_watermark_ranges()
416 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in vg_build_watermark_ranges()
429 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in vg_build_watermark_ranges()
435 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in vg_build_watermark_ranges()
H A Ddcn301_smu.h56 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c436 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn31_build_watermark_ranges()
452 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn31_build_watermark_ranges()
465 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in dcn31_build_watermark_ranges()
471 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in dcn31_build_watermark_ranges()
H A Ddcn31_smu.h52 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_smu.h49 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
H A Ddcn35_clk_mgr.c755 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn35_build_watermark_ranges()
771 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn35_build_watermark_ranges()
784 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in dcn35_build_watermark_ranges()
790 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in dcn35_build_watermark_ranges()
/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c500 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn314_build_watermark_ranges()
516 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn314_build_watermark_ranges()
529 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in dcn314_build_watermark_ranges()
535 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in dcn314_build_watermark_ranges()
/linux-6.15/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu_helper.h36 uint16_t MinClock; member
H A Dsmu_helper.c728 table->WatermarkRow[1][i].MinClock = in smu_set_watermarks_for_clocks_ranges()
749 table->WatermarkRow[0][i].MinClock = in smu_set_watermarks_for_clocks_ranges()
/linux-6.15/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_5_ppt.c424 table->WatermarkRow[WM_DCFCLK][i].MinClock = in smu_v13_0_5_set_watermarks_table()
438 table->WatermarkRow[WM_SOCCLK][i].MinClock = in smu_v13_0_5_set_watermarks_table()
H A Dsmu_v13_0_4_ppt.c678 table->WatermarkRow[WM_DCFCLK][i].MinClock = in smu_v13_0_4_set_watermarks_table()
692 table->WatermarkRow[WM_SOCCLK][i].MinClock = in smu_v13_0_4_set_watermarks_table()
/linux-6.15/drivers/gpu/drm/amd/pm/powerplay/inc/vega12/
H A Dsmu9_driver_if.h574 uint16_t MinClock; member

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