| /linux-6.15/drivers/phy/freescale/ |
| H A D | phy-fsl-imx8qm-lvds-phy.c | 22 #define M_MASK GENMASK(18, 17) macro
23 #define M(n) FIELD_PREP(M_MASK, (n))
39 #define CTRL_INIT_MASK (M_MASK | CCM_MASK | CA_MASK | TST_MASK | NB | RFB)
117 regmap_update_bits(priv->regmap, PHY_CTRL, M_MASK | NB, val); in mixel_lvds_phy_power_on()
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| /linux-6.15/drivers/phy/rockchip/ |
| H A D | phy-rockchip-samsung-dcphy.c | 141 #define M_MASK GENMASK(9, 0) macro
142 #define M(x) FIELD_PREP(M_MASK, x)
1076 M_MASK, M(samsung->pll.fbdiv)); in samsung_mipi_dcphy_pll_configure()
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| /linux-6.15/drivers/gpu/drm/bridge/imx/ |
| H A D | imx93-mipi-dsi.c | 41 #define M_MASK GENMASK(9, 0) macro
42 #define M(x) FIELD_PREP(M_MASK, ((x) - 2))
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| /linux-6.15/drivers/atm/ |
| H A D | iphase.c | 315 #define M_MASK 0x1ff in cellrate_to_float() macro
327 flot = NZ | (i << M_BITS) | (cr & M_MASK); in cellrate_to_float()
329 flot = NZ | (i << M_BITS) | ((cr << (M_BITS - i)) & M_MASK); in cellrate_to_float()
331 flot = NZ | (i << M_BITS) | ((cr >> (i - M_BITS)) & M_MASK); in cellrate_to_float()
346 mantissa = rate & M_MASK;
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| /linux-6.15/arch/powerpc/xmon/ |
| H A D | ppc-opc.c | 2461 #define M_MASK M (0x3f, 1) macro
2471 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
2474 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
4588 {"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4596 {"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4602 {"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
4603 {"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
4606 {"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4607 {"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
7106 {"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}},
[all …]
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| /linux-6.15/drivers/iommu/ |
| H A D | msm_iommu_hw-8xxx.h | 1123 #define M (M_MASK << M_SHIFT)
1585 #define M_MASK 0x01 macro
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