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Searched refs:MTL_GSC_HECI1_BASE (Results 1 – 8 of 8) sorted by relevance

/linux-6.15/drivers/gpu/drm/xe/
H A Dxe_gsc.c183 return xe_mmio_read32(&gt->mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE)) & in gsc_fw_is_loaded()
194 return xe_mmio_wait32(&gt->mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE), in gsc_fw_wait()
630 xe_mmio_read32(mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE)), in xe_gsc_print_info()
631 xe_mmio_read32(mmio, HECI_FWSTS2(MTL_GSC_HECI1_BASE)), in xe_gsc_print_info()
632 xe_mmio_read32(mmio, HECI_FWSTS3(MTL_GSC_HECI1_BASE)), in xe_gsc_print_info()
633 xe_mmio_read32(mmio, HECI_FWSTS4(MTL_GSC_HECI1_BASE)), in xe_gsc_print_info()
634 xe_mmio_read32(mmio, HECI_FWSTS5(MTL_GSC_HECI1_BASE)), in xe_gsc_print_info()
635 xe_mmio_read32(mmio, HECI_FWSTS6(MTL_GSC_HECI1_BASE))); in xe_gsc_print_info()
H A Dxe_gsc_proxy.c68 u32 fwsts1 = xe_mmio_read32(&gt->mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE)); in xe_gsc_proxy_init_done()
79 return xe_mmio_wait32(&gt->mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE), in xe_gsc_wait_for_proxy_init_done()
H A Dxe_huc.c224 HECI_FWSTS5(MTL_GSC_HECI1_BASE),
/linux-6.15/drivers/gpu/drm/xe/regs/
H A Dxe_gsc_regs.h16 #define MTL_GSC_HECI1_BASE 0x00116000 macro
/linux-6.15/drivers/gpu/drm/i915/gt/uc/
H A Dintel_gsc_fw.c19 u32 fw_status = intel_uncore_read(uncore, HECI_FWSTS(MTL_GSC_HECI1_BASE, 1)); in gsc_is_in_reset()
33 fw_status = intel_uncore_read(uncore, HECI_FWSTS(MTL_GSC_HECI1_BASE, 1)); in gsc_uc_get_fw_status()
356 HECI_FWSTS(MTL_GSC_HECI1_BASE, 1), in gsc_fw_wait()
H A Dintel_gsc_uc.c354 HECI_FWSTS(MTL_GSC_HECI1_BASE, i)); in intel_gsc_uc_load_status()
H A Dintel_huc.c314 huc->status[INTEL_HUC_AUTH_BY_GSC].reg = HECI_FWSTS(MTL_GSC_HECI1_BASE, 5); in intel_huc_init_early()
/linux-6.15/drivers/gpu/drm/i915/
H A Di915_reg.h322 #define MTL_GSC_HECI1_BASE 0x00116000 macro