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/linux-6.15/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,msm8996-mss-pil.yaml27 - description: MSS QDSP6 registers
114 within MSS.
216 - description: GCC MSS IFACE clock
217 - description: GCC MSS BUS clock
218 - description: GCC MSS MEM clock
220 - description: GCC MSS GPLL0 clock
253 - description: GCC MSS BUS clock
254 - description: GCC MSS MEM clock
290 - description: GCC MSS BUS clock
291 - description: GCC MSS MEM clock
[all …]
H A Dqcom,sc7180-mss-pil.yaml7 title: Qualcomm SC7180 MSS Peripheral Image Loader
23 - description: MSS QDSP6 registers
56 - description: GCC MSS IFACE clock
57 - description: GCC MSS BUS clock
58 - description: GCC MSS NAV clock
59 - description: GCC MSS SNOC_AXI clock
60 - description: GCC MSS MFAB_AXIS clock
76 - description: MSS power domain
110 within MSS.
152 - description: IRQ from MSS to GLINK
[all …]
H A Dqcom,sc7280-mss-pil.yaml7 title: Qualcomm SC7280 MSS Peripheral Image Loader
23 - description: MSS QDSP6 registers
60 - description: GCC MSS IFACE clock
61 - description: GCC MSS OFFLINE clock
62 - description: GCC MSS SNOC_AXI clock
77 - description: MSS power domain
110 within MSS.
166 - description: IRQ from MSS to GLINK
170 - description: Mailbox for communication between APPS and MSS
H A Dqcom,msm8916-mss-pil.yaml7 title: Qualcomm MSM8916 MSS Peripheral Image Loader (and similar)
33 - description: MSS QDSP6 registers
77 - description: MSS proxy power domain (control handed over after startup)
92 description: MSS power domain supply (only valid for qcom,msm8974-mss-pil)
96 - description: MSS restart control
126 within MSS.
H A Dqcom,sc7180-pas.yaml104 - description: MSS power domain
121 - description: MSS power domain
H A Dqcom,sdx55-pas.yaml41 - description: MSS power domain
H A Dqcom,sm6350-pas.yaml116 - description: MSS power domain
H A Dqcom,sm8150-pas.yaml114 - description: MSS power domain
H A Dqcom,sm8350-pas.yaml96 - description: MSS power domain
/linux-6.15/Documentation/devicetree/bindings/soc/microchip/
H A Dmicrochip,mpfs-sys-controller.yaml7 title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller
35 for Auto Update. The MSS and system controller have separate QSPI
37 MSS can write bitstreams to the flash.
/linux-6.15/tools/testing/selftests/net/packetdrill/
H A Dtcp_ecn_ecn-uses-ect0.pkt18 // Write 1 MSS.
20 // Send 1 MSS with ect0.
H A Dtcp_fast_recovery_prr-ss-ack-below-snd_una-cubic.pkt38 // 2MSS at 5001:7001 cause us to send out 2 more MSS.
H A Dtcp_nagle_sendmsg_msg_more.pkt37 // Test >MSS write will unleash MSS packets but hold on the remaining data.
H A Dtcp_slow_start_slow-start-after-idle.pkt34 // If slow start after idle works properly, we should send 5 MSS here (cwnd/2)
H A Dtcp_fast_recovery_prr-ss-10pkt-lost-1.pkt38 // Write some more, which we will send 1 MSS at a time,
H A Dtcp_sack_sack-shift-sacked-7-5-6-8-9-fack.pkt8 // Establish a connection and send 10 MSS.
H A Dtcp_slow_start_slow-start-fq-ack-per-2pkt.pkt26 // This might change if we cook the initial packet with 10 MSS.
H A Dtcp_sack_sack-shift-sacked-7-3-4-8-9-fack.pkt8 // Establish a connection and send 10 MSS.
H A Dtcp_sack_sack-shift-sacked-2-6-8-3-9-nofack.pkt10 // Establish a connection and send 10 MSS.
/linux-6.15/tools/testing/selftests/net/
H A Dgro.c70 #define MSS (4096 - sizeof(struct tcphdr) - sizeof(struct ipv6hdr)) macro
72 #define NUM_LARGE_PKT (MAX_PAYLOAD / MSS)
374 static char pkts[NUM_LARGE_PKT][TOTAL_HDR_LEN + MSS]; in send_large()
375 static char last[TOTAL_HDR_LEN + MSS]; in send_large()
376 static char new_seg[TOTAL_HDR_LEN + MSS]; in send_large()
380 create_packet(pkts[i], i * MSS, 0, MSS, 0); in send_large()
381 create_packet(last, NUM_LARGE_PKT * MSS, 0, remainder, 0); in send_large()
382 create_packet(new_seg, (NUM_LARGE_PKT + 1) * MSS, 0, remainder, 0); in send_large()
385 write_packet(fd, pkts[i], total_hdr_len + MSS, daddr); in send_large()
1075 int remainder = (MAX_PAYLOAD + offset) % MSS; in gro_sender()
[all …]
/linux-6.15/drivers/staging/gpib/common/
H A Diblib.c373 const unsigned int MSS = status_byte & request_service_bit; in ibrsv2() local
378 if (MSS == 0 && new_reason_for_service) in ibrsv2()
385 (MSS == 0 || (MSS && new_reason_for_service))) { in ibrsv2()
/linux-6.15/Documentation/devicetree/bindings/mailbox/
H A Dmicrochip,mpfs-mailbox.yaml7 title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) mailbox controller
/linux-6.15/drivers/staging/most/dim2/
H A Dreg.h22 u32 MSS; /* 0x08 */ member
/linux-6.15/arch/riscv/boot/dts/microchip/
H A Dmpfs-icicle-kit.dts231 * controller itself can actually access it, but the MSS cannot write
/linux-6.15/Documentation/devicetree/bindings/arm/marvell/
H A Dap80x-system-controller.txt27 - 3: MSS clock, derived from the fixed PLL

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