Home
last modified time | relevance | path

Searched refs:MSI (Results 1 – 25 of 172) sorted by relevance

1234567

/linux-6.15/Documentation/translations/zh_CN/PCI/
H A Dmsi-howto.rst16 MSI驱动指南
26 本指南介绍了消息标记中断（MSI）的基本知识，使用MSI相对于传统中断机制的优势，如何
27 改变你的驱动程序以使用MSI或MSI-X，以及在设备不支持MSI时可以尝试的一些基本诊断方法。
30 什么是MSI?
38 设备可以同时支持MSI和MSI-X，但一次只能启用一个。
76 使用MSI
82 要自动使用MSI或MSI-X中断向量，请使用以下函数::
103 如果一个设备同时支持MSI-X和MSI功能，这个API将优先使用MSI-X，而不是MSI。MSI-X支
105 此外，MSI中断向量必须连续分配，所以系统可能无法为MSI分配像MSI-X那样多的向量。在一
140 以下用于启用和禁用MSI或MSI-X中断的旧API不应该在新代码中使用::
[all …]
H A Dpci.rst293 中断号码代表从PCI设备到中断控制器的IRQ线。在MSI和MSI-X中（更多内容见下文），中
299 MSI和MSI-X是PCI功能。两者都是“消息信号中断”，通过向本地APIC的DMA写入来向CPU发
300 送中断。MSI和MSI-X的根本区别在于如何分配多个“向量”。MSI需要连续的向量块，而
301 MSI-X可以分配几个单独的向量。
305 据编程到PCI设备功能寄存器中。许多架构、芯片组或BIOS不支持MSI或MSI-X，调用
309 对MSI/MSI-X和传统INTx有不同中断处理程序的驱动程序应该在调用
313 使用MSI有（至少）两个真正好的理由：
315 1) 根据定义，MSI是一个排他性的中断向量。这意味着中断处理程序不需要验证其设备是
318 2) MSI避免了DMA/IRQ竞争条件。到主机内存的DMA被保证在MSI交付时对主机CPU是可
323 参见drivers/infiniband/hw/mthca/或drivers/net/tg3.c了解MSI/MSI-X的使
[all …]
H A Dpciebus-howto.rst166 MSI 和 MSI-X 向量资源
169 一旦设备上的MSI或MSI-X中断被启用，它就会一直保持这种模式，直到它们再次被禁用。由于同
171 禁用MSI/MSI-X模式，可能会导致不可预知的行为。
/linux-6.15/Documentation/PCI/
H A Dmsi-howto.rst5 The MSI Driver Guide HOWTO
17 to change your driver to use MSI or MSI-X and some basic diagnostics to
32 Devices may support both MSI and MSI-X, but only one can be enabled at
73 driver has to set up the device to use MSI or MSI-X. Not all machines
86 Using MSI
93 To automatically use MSI or MSI-X interrupt vectors, use the following
122 MSI-X facilities in preference to the MSI facilities. MSI-X supports any
161 the driver can specify that only MSI or MSI-X is acceptable::
184 pci_nr_irq_vectors() helper that handles MSI and MSI-X transparently.
202 How to tell whether MSI/MSI-X is enabled on a device
[all …]
/linux-6.15/Documentation/devicetree/bindings/interrupt-controller/
H A Dmsi.txt1 This document describes the generic device tree binding for MSI controllers and
9 those busses to the MSI controllers which they are capable of using,
22 MSI controllers may have restrictions on permitted payloads.
31 MSI controllers:
40 - msi-controller: Identifies the node as an MSI controller.
51 the specific MSI controller.
54 MSI clients
57 MSI clients are devices which generate MSIs. For each MSI they wish to
68 MSI controllers listed in the msi-parent property.
130 * Has different IDs at each MSI controller.
[all …]
H A Dfsl,ls-msi.yaml7 title: Freescale Layerscape SCFG PCIe MSI controller
16 MSI controller node
38 - description: Shared MSI interrupt group 0
39 - description: Shared MSI interrupt group 1
40 - description: Shared MSI interrupt group 2
41 - description: Shared MSI interrupt group 3
H A Dmsi-controller.yaml7 title: MSI controller
13 An MSI controller signals interrupts to a CPU when a write is made
14 to an MMIO address by some master. An MSI controller may feature a
27 binding of the specific MSI controller.
32 Identifies the node as an MSI controller.
H A Dloongson,pch-msi.yaml7 title: Loongson PCH MSI Controller
14 transforming interrupts from PCIe MSI into HyperTransport vectorized
27 to PCH MSI.
35 to PCH MSI.
H A Dal,alpine-msix.txt3 See arm,gic-v3.txt for SPI and MSI definitions.
12 - al,msi-base-spi: SPI base of the MSI frame
13 - al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0
H A Driscv,imsics.yaml7 title: RISC-V Incoming MSI Controller (IMSIC)
14 MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
32 RISC-V platform. The MSI target address of a IMSIC interrupt file at given
99 Number of guest index bits in the MSI target address.
105 Number of HART index bits in the MSI target address. When not
113 Number of group index bits in the MSI target address.
122 MSI target address.
H A Dmarvell,odmi-controller.txt2 * Marvell ODMI for MSI support
5 which can be used by on-board peripheral for MSI interrupts.
15 - msi-controller : Identifies the node as an MSI controller.
/linux-6.15/Documentation/translations/zh_CN/arch/loongarch/
H A Dirq-chip-model.rst16 断控制器）、PCH-LPC（LS7A芯片组的LPC中断控制器）和PCH-MSI（MSI中断控制器）。
19 全局中断控制器（每个芯片一个，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
28 PCH-LPC/PCH-MSI，然后被HTVECINTC统一收集，再发送到LIOINTC，最后到达CPUINTC::
46 | PCH-PIC | | PCH-MSI |
64 PCH-LPC/PCH-MSI，然后被EIOINTC统一收集，再直接到达CPUINTC::
77 | PCH-PIC | | PCH-MSI |
95 PCH-MSI, 然后V-EIOINTC统一收集，再直接到达CPUINTC::
108 | PCH-PIC | | PCH-MSI |
164 | PCH-PIC | | PCH-MSI |
210 PCH-MSI::
[all …]
/linux-6.15/Documentation/translations/zh_TW/arch/loongarch/
H A Dirq-chip-model.rst16 斷控制器）、PCH-LPC（LS7A芯片組的LPC中斷控制器）和PCH-MSI（MSI中斷控制器）。
19 全局中斷控制器（每個芯片一個，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
28 PCH-LPC/PCH-MSI，然後被HTVECINTC統一收集，再發送到LIOINTC，最後到達CPUINTC::
46 | PCH-PIC | | PCH-MSI |
64 PCH-LPC/PCH-MSI，然後被EIOINTC統一收集，再直接到達CPUINTC::
77 | PCH-PIC | | PCH-MSI |
123 PCH-MSI::
156 - PCH-PIC/PCH-MSI：即《龍芯7A1000橋片用戶手冊》第5章所描述的“中斷控制器”；
/linux-6.15/Documentation/devicetree/bindings/pci/
H A Dpci-msi.txt2 relationship between PCI devices and MSI controllers.
22 For generic MSI bindings, see
38 * msi-controller is a single phandle to an MSI controller
53 the root complex and MSI controller do not pass sideband data with MSI
79 * The sideband data provided to the MSI controller is
107 * The sideband data provided to the MSI controller is
136 * The sideband data provided to the MSI controller is
166 * The sideband data provided to the MSI controller is
210 * The sideband data provided to MSI controller a is the
212 * The sideband data provided to MSI controller b is the
[all …]
H A Dxgene-pci-msi.txt1 * AppliedMicro X-Gene v1 PCIe MSI controller
6 X-Gene v1 PCIe MSI controller block.
7 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
9 registers. These registers include the MSI termination address and data
10 registers as well as the MSI interrupt status registers.
16 Each PCIe node needs to have property msi-parent that points to an MSI
23 + MSI node:
46 + PCIe controller node with msi-parent property pointing to MSI node:
H A Dmediatek-pcie-gen3.yaml16 This PCIe controller supports up to 256 MSI vectors, the MSI hardware
34 |0|1|...|30|31| |0|1|...|30|31| |0|1|...|30|31| (MSI sets)
37 | | | | | | | | | | | | (MSI vectors)
40 (MSI SET0) (MSI SET1) ... (MSI SET7)
42 With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
43 each set has its own address for MSI message, and supports 32 MSI vectors
/linux-6.15/Documentation/PCI/endpoint/
H A Dpci-ntb-function.rst115 MSI/MSI-X vectors (i.e., initialize the MSI/MSI-X Capability in the
118 to the MSI/MSI-X address programmed by the host. The ARGUMENT
120 lower 16 bits) and if MSI or MSI-X should be configured (BIT 16).
178 in order to raise doorbell. EPF NTB can use either MSI or MSI-X to
179 ring doorbell (MSI-X support will be added later). MSI uses same
180 address for all the interrupts and MSI-X can provide different
181 addresses for different interrupts. The MSI/MSI-X address is provided
182 by the host and the address it gives is based on the MSI/MSI-X
186 for both MSI and MSI-X, EPF NTB allocates a separate region in the
188 be mapped to the MSI/MSI-X address provided by the host. If a host
[all …]
H A Dpci-test-function.rst45 Bit 1 raise MSI IRQ
46 Bit 2 raise MSI-X IRQ
82 This register contains the interrupt type (Legacy/MSI) triggered
83 for the READ/WRITE/COPY and raise IRQ (Legacy/MSI) commands.
89 MSI 1
90 MSI-X 2
101 MSI [1 .. 32]
102 MSI-X [1 .. 2048]
/linux-6.15/Documentation/misc-devices/
H A Dpci-endpoint-test.rst17 #) raise MSI IRQ
18 #) raise MSI-X IRQ
36 Tests message signalled interrupts. The MSI number
39 Tests message signalled interrupts. The MSI-X number
43 should be passed as argument (0: Legacy, 1:MSI, 2:MSI-X).
H A Dspear-pcie-gadget.rst42 no_of_msi zero if MSI is not enabled by host. A positive value is the
43 number of MSI vector granted.
58 INTA, MSI or NO_INT). Select MSI only when you have programmed
60 no_of_msi number of MSI vector needed.
62 send_msi write MSI vector to be sent.
142 if MSI is to be used as interrupt, program no of msi vector needed (say4)::
146 select MSI as interrupt type::
148 # echo MSI >> int_type
165 Should return 4 (number of requested MSI vector)
/linux-6.15/drivers/ntb/
H A DKconfig17 bool "MSI Interrupt Support"
20 Support using MSI interrupt forwarding instead of (or in addition to)
21 hardware doorbells. MSI interrupts typically offer lower latency
22 than doorbells and more MSI interrupts can be made available to
24 in the hardware driver for creating the MSI interrupts.
/linux-6.15/Documentation/arch/loongarch/
H A Dirq-chip-model.rst12 in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
24 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
43 | PCH-PIC | | PCH-MSI |
61 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
75 | PCH-PIC | | PCH-MSI |
93 devices interrupts go to PCH-PIC/PCH-MSI and gathered by V-EIOINTC (Virtual
107 | PCH-PIC | | PCH-MSI |
156 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, PCH-MSI interrupts go
171 | PCH-PIC | | PCH-MSI |
217 PCH-MSI::
[all …]
/linux-6.15/Documentation/devicetree/bindings/powerpc/fsl/
H A Dmsi-pic.txt1 * Freescale MSI interrupt controller
8 version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is
17 region must be added because different MSI group has different MSIIR1 offset.
27 optional, without this, all the MSI interrupts can be used.
29 no splitting an individual MSI register or the associated PIC interrupt).
34 is used for MSI messaging. The address of MSIIR in PCI address space is
35 the MSI message address.
84 Freescale MSI driver calculates the address of MSIIR (in the MSI register
85 block) and sets that address as the MSI message address.
/linux-6.15/Documentation/devicetree/bindings/mailbox/
H A Dbrcm,iproc-flexrm-mbox.txt14 - msi-parent: Phandles (and potential Device IDs) to MSI controllers
16 interrupts) to CPU. There is one MSI for each FlexRM ring.
23 The 2nd cell contains MSI completion threshold. This is the
25 one MSI interrupt to CPU.
27 The 3rd cell contains MSI timer value representing time for
31 specified by this cell then it will inject one MSI interrupt
/linux-6.15/Documentation/devicetree/bindings/powerpc/4xx/
H A Dhsta.txt10 Currently only the MSI support is used by Linux using the following
15 - reg : register mapping for the HSTA MSI space
16 - interrupts : ordered interrupt mapping for each MSI in the register

1234567