Home
last modified time | relevance | path

Searched refs:MMIO (Results 1 – 25 of 145) sorted by relevance

123456

/linux-6.15/Documentation/translations/zh_CN/PCI/
H A Dpci.rst54 - 请求MMIO/IOP资源
69 - 释放MMIO/IOP资源
182 - 请求MMIO/IOP资源
227 请求MMIO/IOP资源
241 后确定MMIO和IO端口资源的可用性。
337 - 禁用设备对MMIO/IO端口地址的响应
338 - 释放MMIO/IO端口资源
390 禁止设备对MMIO/IO端口地址做出响应
397 释放MMIO/IO端口资源
485 MMIO空间和“写通知”
[all …]
/linux-6.15/Documentation/translations/zh_CN/userspace-api/accelerators/
H A Docxl.rst72 存上下文、内存映射IO（MMIO）区域的大小等。
76 MMIO chapter
79 OpenCAPI为每个AFU定义了两个MMIO区域：
81 * 全局MMIO区域，保存和整个AFU相关的寄存器。
82 * 每个进程的MMIO区域，对于每个上下文固定大小。
168 一个进程可以mmap每个进程的MMIO区域来和AFU交互。
/linux-6.15/Documentation/devicetree/bindings/misc/
H A Dpvpanic-mmio.txt1 * QEMU PVPANIC MMIO Configuration bindings
4 MMIO Configuration interface on the "virt" machine.
14 - reg: the MMIO region used by the device.
/linux-6.15/Documentation/admin-guide/hw-vuln/
H A Dprocessor_mmio_stale_data.rst2 Processor MMIO Stale Data Vulnerabilities
5 Processor MMIO Stale Data Vulnerabilities are a class of memory-mapped I/O
6 (MMIO) vulnerabilities that can expose data. The sequences of operations for
8 vulnerabilities require the attacker to have access to MMIO, many environments
9 are not affected. System environments using virtualization where MMIO access is
49 processors, MMIO primary reads will return 64 bytes of data to the core fill
57 Some endpoint MMIO registers incorrectly handle writes that are smaller than
145 is more critical, or the untrusted software has no MMIO access). Note that
170 virtualization case, VERW is only needed at VMENTER for a guest with MMIO
190 MDS/TAA, guest without MMIO access cannot extract secrets using Processor MMIO
[all …]
/linux-6.15/Documentation/devicetree/bindings/tpm/
H A Dtcg,tpm-tis-mmio.yaml7 title: MMIO-accessed Trusted Platform Module conforming to TCG TIS specification
15 one of them being LPC (via MMIO). The standard is named:
30 location and length of the MMIO registers, length should be
/linux-6.15/Documentation/userspace-api/accelerators/
H A Docxl.rst69 work with, the size of its MMIO areas, ...
73 MMIO chapter
76 OpenCAPI defines two MMIO areas for each AFU:
78 * the global MMIO area, with registers pertinent to the whole AFU.
79 * a per-process MMIO area, which has a fixed size for each context.
161 MMIO areas, the AFU version, and the PASID for the current context.
178 A process can mmap the per-process MMIO area for interactions with the
/linux-6.15/arch/x86/kernel/cpu/
H A Dcommon.c1217 #define MMIO BIT(1) macro
1240 VULNBL_INTEL_STEPS(INTEL_HASWELL_X, X86_STEP_MAX, MMIO),
1241 VULNBL_INTEL_STEPS(INTEL_BROADWELL_D, X86_STEP_MAX, MMIO),
1243 VULNBL_INTEL_STEPS(INTEL_BROADWELL_X, X86_STEP_MAX, MMIO),
1245 VULNBL_INTEL_STEPS(INTEL_SKYLAKE_X, 0x5, MMIO | RETBLEED | GDS),
1249 VULNBL_INTEL_STEPS(INTEL_KABYLAKE_L, 0xb, MMIO | RETBLEED | GDS | SRBDS),
1251 VULNBL_INTEL_STEPS(INTEL_KABYLAKE, 0xc, MMIO | RETBLEED | GDS | SRBDS),
1258 VULNBL_INTEL_STEPS(INTEL_COMETLAKE_L, 0x0, MMIO | RETBLEED | ITS),
1270 VULNBL_INTEL_STEPS(INTEL_ATOM_TREMONT, X86_STEP_MAX, MMIO | MMIO_SBDS | RFDS),
1271 VULNBL_INTEL_STEPS(INTEL_ATOM_TREMONT_D, X86_STEP_MAX, MMIO | RFDS),
[all …]
/linux-6.15/Documentation/translations/zh_CN/security/tpm/
H A Dtpm_tis.rst16 有一个名为tpm_tis的驱动，覆盖了内存映射（即 MMIO）接口，但后来它被
19 由于历史原因，最初的MMIO驱动被称为tpm_tis，而FIFO驱动的框架被命名为
/linux-6.15/drivers/gpio/
H A DTODO57 driver infrastructure for doing simpler MMIO GPIO devices and there was
86 - Get rid of struct of_mm_gpio_chip altogether: use the generic MMIO
108 Generic MMIO GPIO
110 The GPIO drivers can utilize the generic MMIO helper library in many
111 cases, and the helper library should be as helpful as possible for MMIO
117 dry-code conversions to MMIO GPIO for maintainers to test
119 - Expand the MMIO GPIO or write a new library for regmap-based I/O
123 - Expand the MMIO GPIO or write a new library for port-mapped I/O
131 In the very similar way to Generic MMIO GPIO convert the users which can
133 MMIO case the regmap MMIO with gpio-regmap.c is preferable over gpio-mmio.c.
/linux-6.15/Documentation/devicetree/bindings/bus/
H A Dbaikal,bt1-apb.yaml14 Baikal-T1 CPU or DMAC MMIO requests are handled by the AMBA 3 AXI Interconnect
31 - description: APB EHB MMIO registers
32 - description: APB MMIO region with no any device mapped
/linux-6.15/drivers/misc/pvpanic/
H A DKconfig16 tristate "pvpanic MMIO device support"
19 This driver provides support for the MMIO pvpanic device.
/linux-6.15/Documentation/devicetree/bindings/regmap/
H A Dregmap.txt10 Regmap defaults to little-endian register access on MMIO based
18 of the CPU and a byteswap for MMIO registers (e.g. many Broadcom MIPS
/linux-6.15/Documentation/PCI/
H A Dpci.rst46 - Request MMIO/IOP resources
62 - Release MMIO/IOP resources
183 - Request MMIO/IOP resources
236 Request MMIO/IOP resources
258 (for MMIO ranges) and request_region() (for IO Port ranges).
372 - Disable device from responding to MMIO/IO Port addresses
373 - Release MMIO/IO Port resource(s)
437 Disable Device from responding to MMIO/IO Port addresses
444 Release MMIO/IO Port Resource(s)
541 MMIO Space and "Write Posting"
[all …]
/linux-6.15/Documentation/mhi/
H A Dmhi.rst25 MMIO section in MHI Internals
28 MMIO (Memory mapped IO) consists of a set of registers in the device hardware,
30 Following are the major components of MMIO register space:
160 to access device MMIO register space.
165 programming MMIO registers.
192 the device's MMIO register space. To initialize the MHI in a device,
198 * Programs MHI MMIO registers and sets device into MHI_M0 state.
/linux-6.15/Documentation/translations/ko_KR/
H A Dmemory-barriers.txt121 - 캐시 일관성 vs MMIO.
1833 합니다. 하지만, 느슨한 순서 규칙의 메모리 I/O 윈도우를 통한 MMIO 의 효과를
2520 순서지어집니다. 이는 같은 CPU 쓰레드에 의한 특정 디바이스로의 MMIO
2526 호출된 MMIO 레지스터 쓰기는 해당 락의 획득에 일관적인 순서로 도달할
2533 전송을 시작시키기 위해 MMIO 컨트롤 레지스터에 쓰기를 할 때 DMA
2539 읽기는 이 DMA 수신의 완료를 표시하는 DMA 엔진의 MMIO 상태 레지스터
2544 주변장치로의 두개의 MMIO 레지스터 쓰기가 행해지는데 첫번째 쓰기가
2717 캐시 일관성 VS MMIO
2725 디바이스 버스로 곧바로 향한다는 것입니다. 이 말은 MMIO 액세스는 먼저
2728 MMIO 액세스가 어떤 방식으로든 의존적이라면 해당 캐시는 두 오퍼레이션 사이에
[all …]
/linux-6.15/Documentation/trace/
H A Dmmiotrace.rst10 MMIO tracing was originally developed by Intel around 2003 for their Fault
12 Jeff Muizelaar created a tool for tracing MMIO accesses with the Nouveau
67 Load the driver you want to trace and use it. Mmiotrace will only catch MMIO
126 MMIO accesses are recorded via page faults. Just before __ioremap() returns,
166 zero if it is not recorded. PID is always zero as tracing MMIO accesses
182 - replaying MMIO logs, i.e., re-executing the recorded writes
/linux-6.15/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/
H A Doverview.rst121 A DPRC has a mappable MMIO region (an MC portal) that can be used
172 supports and a summary of key resources of the object (MMIO regions
180 - MMIO regions: none
191 - MMIO regions: none
201 from the queues themselves. The DPIO provides an MMIO interface to
203 to the DPIO MMIO region, which includes the target queue number.
208 - MMIO regions: queue operations, buffer management
217 - MMIO regions: none
227 - MMIO regions: MC command portal
/linux-6.15/drivers/soc/aspeed/
H A DKconfig38 tristate "ASPEED P2A (VGA MMIO to BMC) bridge control"
43 Control ASPEED P2A VGA MMIO to BMC mappings through ioctl()s. The
/linux-6.15/drivers/mux/
H A DKconfig49 tristate "MMIO/Regmap register bitfield-controlled Multiplexer"
52 MMIO/Regmap register bitfield-controlled Multiplexer controller.
/linux-6.15/drivers/net/ethernet/via/
H A DKconfig37 bool "Use MMIO instead of PIO"
40 This instructs the driver to use PCI shared memory (MMIO) instead of
/linux-6.15/Documentation/devicetree/bindings/media/
H A Dnvidia,tegra-vde.yaml69 Phandle of the SRAM MMIO node.
108 iram = <&iram>; /* IRAM MMIO region */
/linux-6.15/Documentation/devicetree/bindings/interrupt-controller/
H A Dmsi.txt5 write to an MMIO address.
14 - The doorbell (the MMIO address written to).
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
/linux-6.15/Documentation/arch/arm64/
H A Darm-cca.rst29 to make changes to the pages in this region, and is able to emulate MMIO
51 * MMIO devices must be either unprotected (e.g. emulated by the Normal
54 * MMIO devices emulated by the Normal World and used very early in boot
/linux-6.15/Documentation/arch/powerpc/
H A Dpci_iov_resource_on_powernv.rst13 This document describes the requirement from hardware for PCI MMIO resource
29 state bits (one for MMIO and one for DMA, they get set together but can be
37 The interesting part is how the various PCIe transactions (MMIO, DMA, ...)
96 maps each segment to a PE#. That allows portions of the MMIO space
101 SR-IOV). We basically use the trick of forcing the bridge MMIO windows
222 The IODA2 platform has 16 M64 windows, which are used to map MMIO
223 range to PE#. Each M64 window defines one MMIO range and this range is
232 device's MMIO range.
236 segments [total_VFs, 255] of the M64 window may map to some MMIO range on
287 In IODA2, the MMIO address determines the PE#. If the address is in an M32
/linux-6.15/Documentation/devicetree/bindings/hwmon/
H A Dbaikal,bt1-pvt.yaml19 control wrapper, which provides a MMIO registers-based access to the
44 like MMIO registers space, interrupt request number and clocks source.

123456