Searched refs:MMC_TIMING_UHS_DDR50 (Results 1 – 25 of 37) sorted by relevance
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31 if (ios->timing == MMC_TIMING_MMC_DDR52 || ios->timing == MMC_TIMING_UHS_DDR50) { in dw_mci_starfive_set_ios()
767 case MMC_TIMING_UHS_DDR50: in sdhci_zynqmp_sdcardclk_set_phase()836 case MMC_TIMING_UHS_DDR50: in sdhci_zynqmp_sampleclk_set_phase()896 case MMC_TIMING_UHS_DDR50: in sdhci_versal_sdcardclk_set_phase()963 case MMC_TIMING_UHS_DDR50: in sdhci_versal_sampleclk_set_phase()1130 if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) in arasan_zynqmp_execute_tuning()1337 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_DDR50, in arasan_dt_parse_clk_phases()
33 ios->timing == MMC_TIMING_UHS_DDR50) in dw_mci_hi3798cv200_set_ios()
266 case MMC_TIMING_UHS_DDR50: in pxav3_set_uhs_signaling()279 uhs == MMC_TIMING_UHS_DDR50) { in pxav3_set_uhs_signaling()
44 || ios->timing == MMC_TIMING_UHS_DDR50) in dw_mci_hi3798mv200_set_ios()
216 else if ((timing == MMC_TIMING_UHS_DDR50) || in xenon_set_uhs_signaling()361 if (host->timing == MMC_TIMING_UHS_DDR50 || in xenon_execute_tuning()
650 case MMC_TIMING_UHS_DDR50: in xenon_emmc_phy_set()784 case MMC_TIMING_UHS_DDR50: in xenon_hs_delay_adj()
1035 case MMC_TIMING_UHS_DDR50: in sd_set_timing()1116 case MMC_TIMING_UHS_DDR50: in sdmmc_set_ios()1336 case MMC_TIMING_UHS_DDR50: in sdmmc_execute_tuning()1351 else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) in sdmmc_execute_tuning()
284 case MMC_TIMING_UHS_DDR50: in arasan_select_phy_clock()
291 case MMC_TIMING_UHS_DDR50: in sdhci_st_set_uhs_signaling()
1114 if (host->timing == MMC_TIMING_UHS_DDR50) in usdhc_execute_tuning()1252 case MMC_TIMING_UHS_DDR50: in esdhc_change_pinstate()1339 case MMC_TIMING_UHS_DDR50: in esdhc_set_uhs_signaling()
180 else if ((timing == MMC_TIMING_UHS_DDR50) || in sdhci_brcmstb_set_uhs_signaling()
750 if (ios->timing != MMC_TIMING_UHS_DDR50) { in usdhi6_clk_set()853 if (ios->timing == MMC_TIMING_UHS_DDR50) in usdhi6_set_ios()860 mode = ios->timing == MMC_TIMING_UHS_DDR50; in usdhi6_set_ios()
830 if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52) in sdhci_omap_set_uhs_signaling()1153 pinctrl_state[MMC_TIMING_UHS_DDR50] = state; in sdhci_omap_config_iodelay_pinctrl_state()
524 if (ios->timing == MMC_TIMING_UHS_DDR50) { in owl_mmc_set_ios()
359 case MMC_TIMING_UHS_DDR50: in dw_mci_exynos_set_ios()
1057 case MMC_TIMING_UHS_DDR50: in sd_set_timing()1121 case MMC_TIMING_UHS_DDR50: in sdmmc_set_ios()
741 if (ios->timing != MMC_TIMING_UHS_DDR50 && in sunxi_mmc_clk_set_phase()891 if (ios->timing == MMC_TIMING_UHS_DDR50 || in sunxi_mmc_set_clk()
303 host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) in mmci_sdmmc_set_clkreg()
1894 case MMC_TIMING_UHS_DDR50: in sdhci_get_preset_value()2318 else if ((timing == MMC_TIMING_UHS_DDR50) || in sdhci_set_uhs_signaling()2334 case MMC_TIMING_UHS_DDR50: in sdhci_timing_has_preset()2449 ios->timing == MMC_TIMING_UHS_DDR50 || in sdhci_set_ios()2951 case MMC_TIMING_UHS_DDR50: in sdhci_execute_tuning()
360 case MMC_TIMING_UHS_DDR50: in sdhci_sprd_set_uhs_signaling()
62 #define MMC_TIMING_UHS_DDR50 7 macro689 card->host->ios.timing <= MMC_TIMING_UHS_DDR50; in mmc_card_uhs()
144 case MMC_TIMING_UHS_DDR50: in mmc_ios_show()
496 timing = MMC_TIMING_UHS_DDR50; in sd_set_bus_speed_mode()669 card->host->ios.timing == MMC_TIMING_UHS_DDR50 || in mmc_sd_init_uhs_card()680 if (err && card->host->ios.timing == MMC_TIMING_UHS_DDR50) { in mmc_sd_init_uhs_card()
252 &map->phase[MMC_TIMING_UHS_DDR50]); in mmc_of_parse_clk_phase()