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Searched refs:MI_LOAD_REGISTER_IMM (Results 1 – 22 of 22) sorted by relevance

/linux-6.15/drivers/gpu/drm/xe/instructions/
H A Dxe_mi_commands.h43 #define MI_LOAD_REGISTER_IMM __MI_INSTR(0x22) macro
/linux-6.15/drivers/gpu/drm/i915/gt/
H A Dintel_ring_submission.c696 *cs++ = MI_LOAD_REGISTER_IMM(1); in load_pd_dir()
700 *cs++ = MI_LOAD_REGISTER_IMM(1); in load_pd_dir()
710 *cs++ = MI_LOAD_REGISTER_IMM(1); in load_pd_dir()
754 *cs++ = MI_LOAD_REGISTER_IMM(num_engines); in mi_set_context()
808 *cs++ = MI_LOAD_REGISTER_IMM(num_engines); in mi_set_context()
854 *cs++ = MI_LOAD_REGISTER_IMM(L3LOG_DW); in remap_l3_slice()
H A Dintel_lrc.c75 *regs = MI_LOAD_REGISTER_IMM(count); in set_offsets()
1334 *cs++ = MI_LOAD_REGISTER_IMM(1); in dg2_emit_draw_watermark_setting()
1344 *cs++ = MI_LOAD_REGISTER_IMM(1); in gen12_invalidate_state_cache()
1647 *batch++ = MI_LOAD_REGISTER_IMM(1); in gen8_emit_flush_coherentl3_wa()
1722 *batch++ = MI_LOAD_REGISTER_IMM(count); in emit_lri()
H A Dselftest_workarounds.c580 *cs++ = MI_LOAD_REGISTER_IMM(1); in check_dirty_whitelist()
593 *cs++ = MI_LOAD_REGISTER_IMM(1); in check_dirty_whitelist()
904 *cs++ = MI_LOAD_REGISTER_IMM(whitelist_writable_count(engine)); in scrub_whitelisted_registers()
H A Dintel_gpu_commands.h155 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1) macro
H A Dgen7_renderclear.c399 batch_add(&cmds, MI_LOAD_REGISTER_IMM(2)); in emit_batch()
H A Dselftest_rps.c101 *cs++ = MI_LOAD_REGISTER_IMM(__NGPR__ * 2); in create_spin_counter()
109 *cs++ = MI_LOAD_REGISTER_IMM(1); in create_spin_counter()
H A Dgen8_engine_cs.c207 *cs++ = MI_LOAD_REGISTER_IMM(1) | MI_LRI_MMIO_REMAP_EN; in gen12_emit_aux_table_inv()
H A Dselftest_lrc.c548 *cs++ = MI_LOAD_REGISTER_IMM(NUM_GPR_DW); in gpr_make_dirty()
1187 *cs++ = MI_LOAD_REGISTER_IMM(len); in load_context()
H A Dselftest_execlists.c3080 *cs++ = MI_LOAD_REGISTER_IMM(1); in create_gpr_user()
4249 *cs++ = MI_LOAD_REGISTER_IMM(1); in preserved_virtual_engine()
H A Dintel_workarounds.c998 *cs++ = MI_LOAD_REGISTER_IMM(wal->count); in intel_engine_emit_ctx_wa()
H A Dintel_execlists_submission.c2744 *cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES) | MI_LRI_FORCE_POSTED; in emit_pdps()
/linux-6.15/drivers/gpu/drm/i915/gvt/
H A Dmmio_context.c230 *cs++ = MI_LOAD_REGISTER_IMM(count); in restore_context_mmio_for_inhibit()
263 *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE); in restore_render_mocs_control_for_inhibit()
290 *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE / 2); in restore_render_mocs_l3cc_for_inhibit()
/linux-6.15/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_client_blt.c161 *cs++ = MI_LOAD_REGISTER_IMM(1); in prepare_blit()
201 *cs++ = MI_LOAD_REGISTER_IMM(1); in prepare_blit()
/linux-6.15/drivers/gpu/drm/i915/
H A Di915_cmd_parser.c228 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
485 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
1292 if (cmd_desc_is(desc, MI_LOAD_REGISTER_IMM(1)) && in check_cmd()
H A Di915_perf.c2023 *cs++ = MI_LOAD_REGISTER_IMM(1); in alloc_noa_wait()
2041 *cs++ = MI_LOAD_REGISTER_IMM(1); in alloc_noa_wait()
2089 *cs++ = MI_LOAD_REGISTER_IMM(2); in alloc_noa_wait()
2170 *cs++ = MI_LOAD_REGISTER_IMM(n_lri); in write_cs_mi_lri()
2519 *cs++ = MI_LOAD_REGISTER_IMM(count); in gen8_load_flex()
/linux-6.15/drivers/gpu/drm/i915/selftests/
H A Di915_perf.c342 *cs++ = MI_LOAD_REGISTER_IMM(32); in live_noa_gpr()
/linux-6.15/drivers/gpu/drm/xe/
H A Dxe_lrc.c136 *regs = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count); in set_offsets()
599 regs[CTX_LRI_INT_REPORT_PTR] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(num_regs) | in set_memory_based_intr()
1415 case MI_LOAD_REGISTER_IMM: in dump_mi_command()
H A Dxe_ring_ops.c56 dw[i++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1) | MI_LRI_MMIO_REMAP_EN; in emit_aux_table_inv()
H A Dxe_gt.c215 bb->cs[bb->len++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count); in emit_wa_job()
H A Dxe_oa.c674 bb->cs[bb->len++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(n_lri); in write_cs_mi_lri()
/linux-6.15/drivers/gpu/drm/i915/gem/
H A Di915_gem_execbuffer.c2234 *cs++ = MI_LOAD_REGISTER_IMM(4); in i915_reset_gen7_sol_offsets()