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/linux-6.15/Documentation/fb/
H A Dviafb.modes29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
116 # D: 52.406 MHz, H: 61.800 kHz, V: 120.00 Hz
137 # D: 26.880 MHz, H: 30.000 kHz, V: 60.24 Hz
158 # D: 29.500 MHz, H: 29.738 kHz, V: 60.00 Hz
179 # D: 32.668 MHz, H: 35.820 kHz, V: 60.00 Hz
200 # D: 40.00 MHz, H: 37.879 kHz, V: 60.32 Hz
[all …]
/linux-6.15/drivers/media/dvb-frontends/
H A Ddvb-pll.c74 .min = 177 * MHz,
75 .max = 858 * MHz,
96 .min = 177 * MHz,
97 .max = 896 * MHz,
120 .min = 185 * MHz,
272 .min = 47 * MHz,
273 .max = 863 * MHz,
290 .min = 54 * MHz,
291 .max = 864 * MHz,
307 .min = 54 * MHz,
[all …]
/linux-6.15/Documentation/userspace-api/media/dvb/
H A Dfe-bandwidth-t.rst34 - 1.712 MHz
42 - 5 MHz
50 - 6 MHz
58 - 7 MHz
66 - 8 MHz
74 - 10 MHz
/linux-6.15/Documentation/devicetree/bindings/mfd/
H A Domap-usb-host.txt40 * "usbhost_120m_fck" - 120MHz Functional clock.
43 * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
53 * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
54 * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
55 * "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate.
56 * "usb_host_hs_hsic60m_p3_clk" - Port 3 60MHz HSIC clock gate.
/linux-6.15/arch/arm64/boot/dts/exynos/
H A Dexynos5433-tmu.dtsi56 /* Set maximum frequency as 1800MHz */
62 /* Set maximum frequency as 1700MHz */
68 /* Set maximum frequency as 1600MHz */
74 /* Set maximum frequency as 1500MHz */
80 /* Set maximum frequency as 1400MHz */
86 /* Set maximum frequencyas 1200MHz */
92 /* Set maximum frequency as 1000MHz */
230 /* Set maximum frequency as 1200MHz */
236 /* Set maximum frequency as 1100MHz */
248 /* Set maximum frequency as 900MHz */
[all …]
/linux-6.15/drivers/staging/sm750fb/
H A Dddk750_chip.c9 #define MHz(x) ((x) * 1000000) macro
40 return MHz(130); in get_mxclk_freq()
101 if (frequency > MHz(336)) in set_memory_clock()
102 frequency = MHz(336); in set_memory_clock()
153 if (frequency > MHz(190)) in set_master_clock()
154 frequency = MHz(190); in set_master_clock()
240 set_chip_clock(MHz((unsigned int)p_init_param->chip_clock)); in ddk750_init_hw()
243 set_memory_clock(MHz(p_init_param->mem_clock)); in ddk750_init_hw()
246 set_master_clock(MHz(p_init_param->master_clock)); in ddk750_init_hw()
/linux-6.15/drivers/media/firewire/
H A Dfiredtv-fe.c173 fi->frequency_min_hz = 950 * MHz; in fdtv_frontend_init()
174 fi->frequency_max_hz = 2150 * MHz; in fdtv_frontend_init()
193 fi->frequency_min_hz = 950 * MHz; in fdtv_frontend_init()
194 fi->frequency_max_hz = 2150 * MHz; in fdtv_frontend_init()
213 fi->frequency_min_hz = 47 * MHz; in fdtv_frontend_init()
214 fi->frequency_max_hz = 866 * MHz; in fdtv_frontend_init()
231 fi->frequency_min_hz = 49 * MHz; in fdtv_frontend_init()
232 fi->frequency_max_hz = 861 * MHz; in fdtv_frontend_init()
/linux-6.15/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos850-clock.yaml73 - description: External reference clock (26 MHz)
89 - description: External reference clock (26 MHz)
107 - description: External reference clock (26 MHz)
125 - description: External reference clock (26 MHz)
143 - description: External reference clock (26 MHz)
167 - description: External reference clock (26 MHz)
187 - description: External reference clock (26 MHz)
207 - description: External reference clock (26 MHz)
225 - description: External reference clock (26 MHz)
243 - description: External reference clock (26 MHz)
[all …]
H A Dsamsung,exynosautov9-clock.yaml20 two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz).
71 - description: External reference clock (26 MHz)
87 - description: External reference clock (26 MHz)
105 - description: External reference clock (26 MHz)
123 - description: External reference clock (26 MHz)
141 - description: External reference clock (26 MHz)
161 - description: External reference clock (26 MHz)
183 - description: External reference clock (26 MHz)
205 - description: External reference clock (26 MHz)
225 - description: External reference clock (26 MHz)
[all …]
H A Dtesla,fsd-clock.yaml16 The root clock comes from external OSC clock (24 MHz).
56 - description: External reference clock (24 MHz)
70 - description: External reference clock (24 MHz)
90 - description: External reference clock (24 MHz)
114 - description: External reference clock (24 MHz)
134 - description: External reference clock (24 MHz)
152 - description: External reference clock (24 MHz)
166 - description: External reference clock (24 MHz)
H A Dstarfive,jh7100-clkgen.yaml22 - description: Main clock source (25 MHz)
23 - description: Application-specific clock source (12-27 MHz)
24 - description: RMII reference clock (50 MHz)
25 - description: RGMII RX clock (125 MHz)
H A Darmada3700-periph-clock.txt36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
H A Dsamsung,exynos2200-cmu.yaml18 are two external clocks: XTCXO (76.8 MHz) and RTCCLK (32768 Hz). XTCXO must be
76 - description: External reference clock (76.8 MHz)
94 - description: External reference clock (76.8 MHz)
114 - description: External reference clock (76.8 MHz)
143 - description: External reference clock (76.8 MHz)
165 - description: External reference clock (25.6 MHz)
185 - description: External reference clock (76.8 MHz)
201 - description: External reference clock (76.8 MHz)
223 - description: External reference clock (76.8 MHz)
H A Dsamsung,exynos7870-cmu.yaml16 is an external clock: OSCCLK (26 MHz). This external clock must be defined
66 - description: External reference clock (26 MHz)
81 - description: External reference clock (26 MHz)
102 - description: External reference clock (26 MHz)
121 - description: External reference clock (26 MHz)
138 - description: External reference clock (26 MHz)
159 - description: External reference clock (26 MHz)
178 - description: External reference clock (26 MHz)
H A Dsamsung,exynos8895-clock.yaml18 is an external clock: OSCCLK (26 MHz). This external clock must be defined
72 - description: External reference clock (26 MHz)
98 - description: External reference clock (26 MHz)
122 - description: External reference clock (26 MHz)
150 - description: External reference clock (26 MHz)
196 - description: External reference clock (26 MHz)
214 - description: External reference clock (26 MHz)
H A Dsophgo,sg2042-pll.yaml21 - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz)
22 - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz)
23 - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz)
/linux-6.15/arch/arm/boot/dts/arm/
H A Dintegratorcp.dts49 /* The codec chrystal operates at 24.576 MHz */
65 /* This is a 25MHz chrystal on the base board */
72 /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
87 /* 24 MHz chrystal on the core module */
124 /* The KMI clock is the 24 MHz oscillator divided to 8MHz */
133 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
149 /* TIMER0 runs directly on the 25MHz chrystal */
155 /* TIMER1 runs @ 1MHz */
161 /* TIMER2 runs @ 1MHz */
297 /* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */
/linux-6.15/drivers/media/tuners/
H A Dqt1010_priv.h70 #define QT1010_MIN_FREQ (48 * MHz)
71 #define QT1010_MAX_FREQ (860 * MHz)
72 #define QT1010_OFFSET (1246 * MHz)
/linux-6.15/arch/arm/boot/dts/rockchip/
H A Drk3288-veyron-mickey.dts86 * and don't let the GPU go faster than 400 MHz.
106 * - 800 MHz (hot)
107 * - 800 MHz - 696 MHz (hotter)
108 * - 696 MHz - min (very hot)
111 * - 800 MHz appears to be a "sweet spot" for me. I can run
113 * - After 696 MHz we stop lowering voltage, so throttling
139 /* At very hot, don't let GPU go over 300 MHz */
180 /* After 1st level throttle the GPU down to as low as 400 MHz */
200 /* When hot, GPU goes down to 300 MHz */
206 /* When really hot, don't let GPU go _above_ 300 MHz */
/linux-6.15/Documentation/admin-guide/pm/
H A Dintel-speed-select.rst154 base-frequency(MHz):2600
183 base-frequency(MHz):2800
424 Specify clos min in MHz with [--min|-n]
467 clos-min:0 MHz
469 clos-desired:0 MHz
477 clos-min:0 MHz
479 clos-desired:0 MHz
620 full guaranteed frequency of 2600 MHz.
651 400 MHz.
700 observed that the high priority CPUs reached 3000 MHz compared to 2600 MHz.
[all …]
/linux-6.15/Documentation/devicetree/bindings/media/i2c/
H A Dsony,imx412.yaml30 description: Clock frequency 6MHz, 12MHz, 18MHz, 24MHz or 27MHz
H A Dsony,imx415.yaml31 description: Input clock (24 MHz, 27 MHz, 37.125 MHz, 72 MHz or 74.25 MHz)
/linux-6.15/Documentation/devicetree/bindings/net/
H A Dti,dp83822.yaml87 - RMII master, where the PHY outputs a 50MHz reference clock which can
89 - RMII slave, where the PHY expects a 50MHz reference clock input
105 - 'mac-if': In MII mode the clock frequency is 25-MHz, in RMII Mode the
106 clock frequency is 50-MHz and in RGMII Mode the clock frequency is
107 25-MHz.
109 - 'int-ref': Internal reference clock 25-MHz.
110 - 'rmii-master-mode-ref': RMII master mode reference clock 50-MHz. RMII
113 - 'free-running': Free running clock 125-MHz.
114 - 'recovered': Recovered clock is a 125-MHz recovered clock from a
H A Dadi,adin.yaml42 A 25MHz reference and a free-running 125MHz.
44 the 125MHz clocks based on its internal state.
52 description: Enable 25MHz reference clock output on CLK25_REF pin.
/linux-6.15/Documentation/userspace-api/media/drivers/
H A Dmax2175.rst53 samples/sec with a 10.24 MHz sck.
56 samples/sec with a 32.768 MHz sck.
61 samples/sec with a 14.88375 MHz sck.
64 samples/sec with a 7.441875 MHz sck.

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