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Searched refs:MHZ (Results 1 – 25 of 92) sorted by relevance

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/linux-6.15/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_mipi_dsi.c102 { MHZ(80), 0x00 }, { MHZ(90), 0x10 }, { MHZ(100), 0x20 },
103 { MHZ(110), 0x30 }, { MHZ(120), 0x01 }, { MHZ(130), 0x11 },
104 { MHZ(140), 0x21 }, { MHZ(150), 0x31 }, { MHZ(160), 0x02 },
105 { MHZ(170), 0x12 }, { MHZ(180), 0x22 }, { MHZ(190), 0x32 },
106 { MHZ(205), 0x03 }, { MHZ(220), 0x13 }, { MHZ(235), 0x23 },
107 { MHZ(250), 0x33 }, { MHZ(275), 0x04 }, { MHZ(300), 0x14 },
108 { MHZ(325), 0x25 }, { MHZ(350), 0x35 }, { MHZ(400), 0x05 },
109 { MHZ(450), 0x16 }, { MHZ(500), 0x26 }, { MHZ(550), 0x37 },
110 { MHZ(600), 0x07 }, { MHZ(650), 0x18 }, { MHZ(700), 0x28 },
111 { MHZ(750), 0x39 }, { MHZ(800), 0x09 }, { MHZ(850), 0x19 },
[all …]
/linux-6.15/drivers/clk/samsung/
H A Dclk-exynos3250.c673 PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
674 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
675 PLL_35XX_RATE(24 * MHZ, 1066000000, 533, 6, 1),
676 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
677 PLL_35XX_RATE(24 * MHZ, 960000000, 320, 4, 1),
678 PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
679 PLL_35XX_RATE(24 * MHZ, 850000000, 425, 6, 1),
680 PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
681 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
683 PLL_35XX_RATE(24 * MHZ, 600000000, 400, 4, 2),
[all …]
H A Dclk-exynos4.c1109 PLL_35XX_RATE(24 * MHZ, 1704000000, 213, 3, 0),
1110 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
1111 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
1112 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
1113 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
1114 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0),
1115 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0),
1116 PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0),
1117 PLL_35XX_RATE(24 * MHZ, 900000000, 150, 4, 0),
1118 PLL_35XX_RATE(24 * MHZ, 800000000, 100, 3, 0),
[all …]
H A Dclk-exynos5420.c1404 PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0),
1405 PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0),
1406 PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0),
1426 PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1),
1427 PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1),
1428 PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1),
1429 PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2),
1430 PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2),
1431 PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3),
1432 PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3),
[all …]
H A Dclk-exynos5250.c697 PLL_36XX_RATE(24 * MHZ, 70500000, 94, 2, 4, 0),
718 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
719 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
726 PLL_35XX_RATE(24 * MHZ, 900000000, 150, 4, 0),
727 PLL_35XX_RATE(24 * MHZ, 800000000, 100, 3, 0),
728 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
729 PLL_35XX_RATE(24 * MHZ, 600000000, 200, 4, 1),
730 PLL_35XX_RATE(24 * MHZ, 500000000, 125, 3, 1),
731 PLL_35XX_RATE(24 * MHZ, 400000000, 100, 3, 1),
732 PLL_35XX_RATE(24 * MHZ, 300000000, 200, 4, 2),
[all …]
H A Dclk-exynos5260.c35 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
36 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
37 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
38 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
43 PLL_35XX_RATE(24 * MHZ, 933000000, 311, 4, 1),
44 PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
45 PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
47 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
49 PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1),
50 PLL_35XX_RATE(24 * MHZ, 620000000, 310, 3, 2),
[all …]
H A Dclk-exynos5410.c228 PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
229 PLL_36XX_RATE(24 * MHZ, 333000000U, 111, 2, 2, 0),
230 PLL_36XX_RATE(24 * MHZ, 300000000U, 100, 2, 2, 0),
231 PLL_36XX_RATE(24 * MHZ, 266000000U, 266, 3, 3, 0),
232 PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0),
233 PLL_36XX_RATE(24 * MHZ, 192000000U, 192, 3, 3, 0),
234 PLL_36XX_RATE(24 * MHZ, 166000000U, 166, 3, 3, 0),
235 PLL_36XX_RATE(24 * MHZ, 133000000U, 266, 3, 4, 0),
236 PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0),
237 PLL_36XX_RATE(24 * MHZ, 66000000U, 176, 2, 5, 0),
[all …]
H A Dclk-exynos5433.c736 PLL_35XX_RATE(24 * MHZ, 2500000000U, 625, 6, 0),
737 PLL_35XX_RATE(24 * MHZ, 2400000000U, 500, 5, 0),
738 PLL_35XX_RATE(24 * MHZ, 2300000000U, 575, 6, 0),
739 PLL_35XX_RATE(24 * MHZ, 2200000000U, 550, 6, 0),
740 PLL_35XX_RATE(24 * MHZ, 2100000000U, 350, 4, 0),
741 PLL_35XX_RATE(24 * MHZ, 2000000000U, 500, 6, 0),
742 PLL_35XX_RATE(24 * MHZ, 1900000000U, 475, 6, 0),
743 PLL_35XX_RATE(24 * MHZ, 1800000000U, 375, 5, 0),
744 PLL_35XX_RATE(24 * MHZ, 1700000000U, 425, 6, 0),
745 PLL_35XX_RATE(24 * MHZ, 1600000000U, 400, 6, 0),
[all …]
/linux-6.15/drivers/clk/mediatek/
H A Dclk-mt8365-apmixedsys.c15 #define MT8365_PLL_FMAX (3800UL * MHZ)
57 { .div = 1, .freq = 1500 * MHZ },
58 { .div = 2, .freq = 750 * MHZ },
59 { .div = 3, .freq = 375 * MHZ },
66 { .div = 1, .freq = 1600 * MHZ },
67 { .div = 2, .freq = 800 * MHZ },
68 { .div = 3, .freq = 400 * MHZ },
69 { .div = 4, .freq = 200 * MHZ },
76 { .div = 2, .freq = 600 * MHZ },
77 { .div = 3, .freq = 400 * MHZ },
[all …]
H A Dclk-mt8183-apmixedsys.c51 #define MT8183_PLL_FMAX (3800UL * MHZ)
52 #define MT8183_PLL_FMIN (1500UL * MHZ)
94 { .div = 1, .freq = 1500 * MHZ },
95 { .div = 2, .freq = 750 * MHZ },
96 { .div = 3, .freq = 375 * MHZ },
103 { .div = 1, .freq = 1600 * MHZ },
104 { .div = 2, .freq = 800 * MHZ },
105 { .div = 3, .freq = 400 * MHZ },
106 { .div = 4, .freq = 200 * MHZ },
H A Dclk-mt2701.c29 108 * MHZ),
31 400 * MHZ),
35 340 * MHZ),
37 340 * MHZ),
39 340 * MHZ),
41 27 * MHZ),
43 416 * MHZ),
45 143 * MHZ),
47 27 * MHZ),
918 #define MT8590_PLL_FMAX (2000 * MHZ)
/linux-6.15/Documentation/userspace-api/media/dvb/
H A Dfe-bandwidth-t.rst30 - .. _BANDWIDTH-1-712-MHZ:
38 - .. _BANDWIDTH-5-MHZ:
46 - .. _BANDWIDTH-6-MHZ:
54 - .. _BANDWIDTH-7-MHZ:
62 - .. _BANDWIDTH-8-MHZ:
70 - .. _BANDWIDTH-10-MHZ:
/linux-6.15/drivers/clk/
H A Dclk-nspire.c13 #define MHZ (1000 * 1000) macro
44 clk->base_clock = 48 * MHZ; in nspire_clkinfo_cx()
46 clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ; in nspire_clkinfo_cx()
55 clk->base_clock = 27 * MHZ; in nspire_clkinfo_classic()
57 clk->base_clock = (300 - 6 * EXTRACT(val, CLASSIC_BASE)) * MHZ; in nspire_clkinfo_classic()
132 info.base_clock / MHZ, in nspire_clk_setup()
133 info.base_clock / info.base_cpu_ratio / MHZ, in nspire_clk_setup()
134 info.base_clock / info.base_ahb_ratio / MHZ); in nspire_clk_setup()
/linux-6.15/drivers/net/can/softing/
H A Dsofting_cs.c26 #define MHZ (1000*1000) macro
33 .freq = 16 * MHZ, .max_brp = 32, .max_sjw = 4,
45 .freq = 16 * MHZ, .max_brp = 32, .max_sjw = 4,
57 .freq = 20 * MHZ, .max_brp = 32, .max_sjw = 4,
69 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
81 .freq = 16 * MHZ, .max_brp = 64, .max_sjw = 4,
93 .freq = 20 * MHZ, .max_brp = 32, .max_sjw = 4,
105 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
117 .freq = 16 * MHZ, .max_brp = 64, .max_sjw = 4,
129 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
/linux-6.15/arch/arm/mach-s3c/
H A Dcpu.h45 #ifndef MHZ
46 #define MHZ (1000*1000) macro
49 #define print_mhz(m) ((m) / MHZ), (((m) / 1000) % 1000)
H A Dsetup-usb-phy-s3c64xx.c36 case 12 * MHZ: in s3c_usb_otgphy_init()
39 case 24 * MHZ: in s3c_usb_otgphy_init()
43 case 48 * MHZ: in s3c_usb_otgphy_init()
/linux-6.15/drivers/gpu/drm/bridge/imx/
H A Dimx93-mipi-dsi.c73 #define MHZ(x) ((x) * 1000000UL) macro
75 #define REF_CLK_RATE_MAX MHZ(64)
76 #define REF_CLK_RATE_MIN MHZ(2)
77 #define FOUT_MAX MHZ(1250)
78 #define FOUT_MIN MHZ(40)
79 #define FVCO_DIV_FACTOR MHZ(80)
250 min_n = DIV_ROUND_UP_ULL((u64)fin, MHZ(8)); in dphy_pll_get_configure_from_opts()
251 max_n = DIV_ROUND_DOWN_ULL((u64)fin, MHZ(2)); in dphy_pll_get_configure_from_opts()
317 return (clk_get_rate(dsi->clk_cfg) / MHZ(1) - 17) * 4; in dphy_pll_get_cfgclkrange()
323 unsigned long mbps = dphy_opts->hs_clk_rate / MHZ(1); in dphy_pll_get_hsfreqrange()
[all …]
/linux-6.15/arch/arm64/boot/dts/qcom/
H A Dipq9574-rdp-common.dtsi169 * (48 MHZ or 96 MHZ used for different RDP type board). This setting
171 * clock output from WiFi to the CMN PLL is 48 MHZ.
179 * The frequency of xo_board_clk is fixed to 24 MHZ, which is routed
180 * from WiFi output clock 48 MHZ divided by 2.
/linux-6.15/drivers/phy/samsung/
H A Dphy-exynos4x12-usb2.c140 case 10 * MHZ: in exynos4x12_rate_to_clk()
143 case 12 * MHZ: in exynos4x12_rate_to_clk()
149 case 20 * MHZ: in exynos4x12_rate_to_clk()
152 case 24 * MHZ: in exynos4x12_rate_to_clk()
155 case 50 * MHZ: in exynos4x12_rate_to_clk()
H A Dphy-s5pv210-usb2.c73 case 12 * MHZ: in s5pv210_rate_to_clk()
76 case 24 * MHZ: in s5pv210_rate_to_clk()
79 case 48 * MHZ: in s5pv210_rate_to_clk()
/linux-6.15/drivers/phy/freescale/
H A Dphy-fsl-samsung-hdmi.c43 #ifndef MHZ
44 #define MHZ (1000UL * 1000UL) macro
340 if (int_pllclk < (50 * MHZ)) in fsl_samsung_hdmi_phy_configure_pll_lock_det()
361 fld_tg_code = DIV_ROUND_UP(24 * MHZ * 256, int_pllclk); in fsl_samsung_hdmi_phy_configure_pll_lock_det()
409 do_div(tmp, 24 * MHZ); in fsl_samsung_hdmi_phy_find_pms()
421 tmp = div64_ul((u64)_m * 24 * MHZ, _p); in fsl_samsung_hdmi_phy_find_pms()
422 if (tmp < 750 * MHZ || in fsl_samsung_hdmi_phy_find_pms()
423 tmp > 3000 * MHZ) in fsl_samsung_hdmi_phy_find_pms()
/linux-6.15/drivers/gpu/drm/bridge/
H A Dsamsung-dsim.c560 #ifndef MHZ
561 #define MHZ (1000 * 1000) macro
578 p_max = fin / (driver_data->pll_fin_min * MHZ); in samsung_dsim_pll_find_pms()
593 if (tmp < driver_data->min_freq * MHZ || in samsung_dsim_pll_find_pms()
594 tmp > driver_data->max_freq * MHZ) in samsung_dsim_pll_find_pms()
637 while (fin > driver_data->pll_fin_max * MHZ) in samsung_dsim_set_pll()
663 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ, in samsung_dsim_set_pll()
664 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ, in samsung_dsim_set_pll()
665 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ, in samsung_dsim_set_pll()
666 770 * MHZ, 870 * MHZ, 950 * MHZ, in samsung_dsim_set_pll()
[all …]
/linux-6.15/arch/powerpc/boot/
H A Dredboot-8xx.c19 #define MHZ(x) ((x + 500000) / 1000000) macro
32 bd.bi_busfreq, MHZ(bd.bi_busfreq)); in platform_fixups()
H A Dredboot-83xx.c20 #define MHZ(x) ((x + 500000) / 1000000) macro
33 bd.bi_busfreq, MHZ(bd.bi_busfreq)); in platform_fixups()
/linux-6.15/drivers/clk/hisilicon/
H A Dclk-hi3660-stub.c25 #define MHZ (1000 * 1000) macro
66 stub_clk->rate = readl(freq_reg + (stub_clk->id << 2)) * MHZ; in hi3660_stub_clk_recalc_rate()
86 stub_clk->msg[1] = rate / MHZ; in hi3660_stub_clk_set_rate()

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