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Searched refs:MDIO_MMD_VEND2 (Results 1 – 25 of 33) sorted by relevance

12

/linux-6.15/drivers/net/pcs/
H A Dpcs-xpcs-nxp.c74 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL2, in nxp_sja1105_sgmii_pma_config()
89 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_TXPLL_CTRL0, in nxp_sja1110_pma_config()
94 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_TXPLL_CTRL1, in nxp_sja1110_pma_config()
100 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_DRIVER1_0, in nxp_sja1110_pma_config()
107 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_DRIVER2_0, val); in nxp_sja1110_pma_config()
122 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_TRIM, val); in nxp_sja1110_pma_config()
127 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_DATAPATH_1, 0); in nxp_sja1110_pma_config()
134 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_RXPLL_CTRL0, in nxp_sja1110_pma_config()
139 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_RXPLL_CTRL1, in nxp_sja1110_pma_config()
155 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, SJA1110_POWERDOWN_ENABLE, in nxp_sja1110_pma_config()
[all …]
H A Dpcs-xpcs.c247 dev = MDIO_MMD_VEND2; in xpcs_soft_reset()
679 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, in xpcs_config_aneg_c37_sgmii()
720 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, in xpcs_config_aneg_c37_sgmii()
747 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, in xpcs_config_aneg_c37_1000basex()
772 ret = xpcs_modify_changed(xpcs, MDIO_MMD_VEND2, in xpcs_config_aneg_c37_1000basex()
786 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, in xpcs_config_aneg_c37_1000basex()
806 return xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, in xpcs_config_2500basex()
1032 lpa = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_LPA); in xpcs_get_state_c37_1000basex()
1036 bmsr = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMSR); in xpcs_get_state_c37_1000basex()
1062 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMSR); in xpcs_get_state_2500basex()
[all …]
H A Dpcs-xpcs-plat.c173 return xpcs_mmio_read_reg_indirect(pxpcs, MDIO_MMD_VEND2, reg); in xpcs_mmio_read_c22()
175 return xpcs_mmio_read_reg_direct(pxpcs, MDIO_MMD_VEND2, reg); in xpcs_mmio_read_c22()
186 return xpcs_mmio_write_reg_indirect(pxpcs, MDIO_MMD_VEND2, reg, val); in xpcs_mmio_write_c22()
188 return xpcs_mmio_write_reg_direct(pxpcs, MDIO_MMD_VEND2, reg, val); in xpcs_mmio_write_c22()
H A Dpcs-lynx.c66 status = mdiobus_c45_read(bus, addr, MDIO_MMD_VEND2, MII_BMSR); in lynx_pcs_get_state_usxgmii()
75 lpa = mdiobus_c45_read(bus, addr, MDIO_MMD_VEND2, MII_LPA); in lynx_pcs_get_state_usxgmii()
185 return mdiobus_c45_write(bus, addr, MDIO_MMD_VEND2, MII_ADVERTISE, in lynx_pcs_config_usxgmii()
/linux-6.15/drivers/net/phy/
H A Ddp83td510.c476 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
482 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
488 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
493 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
555 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_read_status()
644 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_CTRL, in dp83td510_cable_test_start()
680 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG2, in dp83td510_cable_test_start()
704 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG3, in dp83td510_cable_test_start()
709 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_CTRL, in dp83td510_cable_test_start()
733 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG); in dp83td510_cable_test_get_tdr_status()
[all …]
H A Ddp83tg720.c163 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_PKT_STAT_1); in dp83tg720_update_stats()
169 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_PKT_STAT_2); in dp83tg720_update_stats()
176 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_PKT_STAT_3); in dp83tg720_update_stats()
244 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in dp83tg720_cable_test_start()
249 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG2, in dp83tg720_cable_test_start()
254 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG3, in dp83tg720_cable_test_start()
259 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG4, in dp83tg720_cable_test_start()
301 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG); in dp83tg720_cable_test_get_status()
314 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, in dp83tg720_cable_test_get_status()
471 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, in dp83tg720_config_rgmii_delay()
[all …]
H A Ddp83822.c230 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, in dp83822_config_wol()
238 phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83822_config_wol()
241 phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83822_config_wol()
244 phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83822_config_wol()
258 return phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83822_config_wol()
261 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in dp83822_config_wol()
560 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in dp83822_config_init()
621 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in dp83822_config_init()
1051 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, in dp83822_led_hw_control_set()
1055 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, in dp83822_led_hw_control_set()
[all …]
H A Dmicrochip_t1s.c124 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_ADDR, in lan865x_revb_indirect_read()
168 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, in lan865x_read_cfg_params()
185 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, cfg_regs[i], in lan865x_write_cfg_params()
249 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in lan865x_revb_config_init()
267 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in lan865x_revb_config_init()
284 err = phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN867X_REG_STS2); in lan867x_check_reset_complete()
290 err = phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN867X_REG_STS2); in lan867x_check_reset_complete()
326 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in lan867x_revc_config_init()
344 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in lan867x_revc_config_init()
369 err = phy_modify_mmd(phydev, MDIO_MMD_VEND2, in lan867x_revb1_config_init()
[all …]
H A Dintel-xway.c254 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, in xway_gphy_init_leds()
258 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL, in xway_gphy_init_leds()
271 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, ledxh); in xway_gphy_init_leds()
272 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, ledxl); in xway_gphy_init_leds()
273 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, ledxh); in xway_gphy_init_leds()
274 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, ledxl); in xway_gphy_init_leds()
275 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, ledxh); in xway_gphy_init_leds()
276 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, ledxl); in xway_gphy_init_leds()
387 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDxH(index), 0); in xway_gphy_led_brightness_set()
435 hval = phy_read_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDxH(index)); in xway_gphy_led_hw_control_get()
[all …]
H A Dmarvell10g.c195 return phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP); in mv3310_hwmon_read_temp_reg()
252 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP, in mv3310_hwmon_config()
259 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL, in mv3310_hwmon_config()
1318 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_WOL_CTRL); in mv3110_get_wol()
1333 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
1340 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
1347 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
1354 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
1362 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
1370 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
[all …]
H A Dphy-c45.c1291 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_IDVER); in genphy_c45_plca_get_cfg()
1300 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL0); in genphy_c45_plca_get_cfg()
1306 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL1); in genphy_c45_plca_get_cfg()
1313 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR); in genphy_c45_plca_get_cfg()
1352 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1367 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1384 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1392 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1407 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1424 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
[all …]
H A Dair_en8811h.c552 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, in air_hw_led_on_set()
579 return phy_write_mmd(phydev, MDIO_MMD_VEND2, in air_hw_led_blink_set()
709 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index), in air_led_hw_control_set()
715 return phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BLINK(index), in air_led_hw_control_set()
737 err = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index), in air_led_init()
752 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_BLINK, in air_leds_init()
757 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_ON, in air_leds_init()
764 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR, in air_leds_init()
771 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR, in air_leds_init()
H A Dmarvell-88x2222.c78 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PORT_RST, in mv2222_soft_reset()
83 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND2, MV_PORT_RST, in mv2222_soft_reset()
199 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
202 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
205 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
H A Dadin1100.c148 int rc = phy_read_mmd(phydev, MDIO_MMD_VEND2, in adin_phy_ack_intr()
168 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, in adin_config_intr()
177 irq_status = phy_read_mmd(phydev, MDIO_MMD_VEND2, in adin_phy_handle_interrupt()
H A Dncn26000.c45 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR, in ncn26000_config_init()
H A Dmxl-gpy.c721 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
728 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
735 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
748 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
764 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
/linux-6.15/drivers/net/ethernet/microchip/
H A Dlan743x_ethtool.c1223 { ETH_SR_MII_CTRL, MDIO_MMD_VEND2, 0x0000}, in lan743x_sgmii_regs()
1224 { ETH_SR_MII_STS, MDIO_MMD_VEND2, 0x0001}, in lan743x_sgmii_regs()
1225 { ETH_SR_MII_DEV_ID1, MDIO_MMD_VEND2, 0x0002}, in lan743x_sgmii_regs()
1226 { ETH_SR_MII_DEV_ID2, MDIO_MMD_VEND2, 0x0003}, in lan743x_sgmii_regs()
1227 { ETH_SR_MII_AN_ADV, MDIO_MMD_VEND2, 0x0004}, in lan743x_sgmii_regs()
1228 { ETH_SR_MII_LP_BABL, MDIO_MMD_VEND2, 0x0005}, in lan743x_sgmii_regs()
1229 { ETH_SR_MII_EXPN, MDIO_MMD_VEND2, 0x0006}, in lan743x_sgmii_regs()
1230 { ETH_SR_MII_EXT_STS, MDIO_MMD_VEND2, 0x000F}, in lan743x_sgmii_regs()
1231 { ETH_SR_MII_TIME_SYNC_ABL, MDIO_MMD_VEND2, 0x0708}, in lan743x_sgmii_regs()
1232 { ETH_SR_MII_TIME_SYNC_TX_MAX_DLY_LWR, MDIO_MMD_VEND2, 0x0709}, in lan743x_sgmii_regs()
[all …]
H A Dlan743x_main.c1040 mpllctrl0 = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, in lan743x_sgmii_mpll_set()
1056 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_sgmii_mpll_set()
1061 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_sgmii_mpll_set()
1066 return lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_sgmii_mpll_set()
1107 dgt_ctrl = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, in lan743x_serdes_clock_and_aneg_update()
1123 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_serdes_clock_and_aneg_update()
1134 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, MII_BMCR, in lan743x_serdes_clock_and_aneg_update()
1139 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_serdes_clock_and_aneg_update()
1144 return lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_serdes_clock_and_aneg_update()
1154 dig_sts = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, in lan743x_pcs_seq_state()
[all …]
/linux-6.15/drivers/net/phy/realtek/
H A Drealtek_hwmon.c33 raw = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL822X_VND2_TSRR) & 0x3ff; in rtl822x_hwmon_read()
38 raw = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL822X_VND2_TSSR) >> 6; in rtl822x_hwmon_read()
68 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, RTL822X_VND2_TSALRM, 3); in rtl822x_hwmon_init()
H A Drealtek_main.c755 return __mdiobus_c45_read(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum); in rtlgen_read_vend2()
760 return __mdiobus_c45_write(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum, in rtlgen_write_vend2()
768 if (devnum == MDIO_MMD_VEND2) in rtlgen_read_mmd()
787 if (devnum == MDIO_MMD_VEND2) in rtlgen_write_mmd()
919 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_PMA_SPEED); in rtl822x_get_features()
940 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, in rtl822x_config_aneg()
987 lpadv = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_AN_10GBT_STAT); in rtl822x_read_status()
1034 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, in rtl822x_c45_config_aneg()
1051 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, in rtl822x_c45_read_status()
1070 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_VND2_PHYSR); in rtl822x_c45_read_status()
/linux-6.15/drivers/net/phy/mediatek/
H A Dmtk-phy-lib.c127 on = phy_read_mmd(phydev, MDIO_MMD_VEND2, in mtk_phy_led_hw_ctrl_get()
133 blink = phy_read_mmd(phydev, MDIO_MMD_VEND2, in mtk_phy_led_hw_ctrl_get()
255 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? in mtk_phy_led_hw_ctrl_set()
263 return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? in mtk_phy_led_hw_ctrl_set()
300 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? in mtk_phy_hw_led_on_set()
325 return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? in mtk_phy_hw_led_blink_set()
/linux-6.15/drivers/net/dsa/sja1105/
H A Dsja1105_mdio.c20 if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2) in sja1105_pcs_mdio_read_c45()
23 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID1) in sja1105_pcs_mdio_read_c45()
25 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID2) in sja1105_pcs_mdio_read_c45()
46 if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2) in sja1105_pcs_mdio_write_c45()
67 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID1) in sja1110_pcs_mdio_read_c45()
69 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID2) in sja1110_pcs_mdio_read_c45()
/linux-6.15/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-mdio.c151 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT); in xgbe_an37_clear_interrupts()
153 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg); in xgbe_an37_clear_interrupts()
160 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); in xgbe_an37_disable_interrupts()
162 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); in xgbe_an37_disable_interrupts()
177 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); in xgbe_an37_enable_interrupts()
179 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); in xgbe_an37_enable_interrupts()
368 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1); in xgbe_an37_set()
377 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg); in xgbe_an37_set()
663 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT); in xgbe_an37_isr()
985 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); in xgbe_an37_init()
[all …]
/linux-6.15/include/uapi/linux/
H A Dmdio.h29 #define MDIO_MMD_VEND2 31 /* Vendor specific 2 */ macro
161 #define MDIO_DEVS_VEND2 MDIO_DEVS_PRESENT(MDIO_MMD_VEND2)
/linux-6.15/rust/kernel/net/phy/
H A Dreg.rs173 pub const VEND2: Self = Mmd(uapi::MDIO_MMD_VEND2 as u8);

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