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Searched refs:MDIO_MMD_VEND1 (Results 1 – 25 of 27) sorted by relevance

12

/linux-6.15/drivers/net/phy/
H A Dnxp-c45-tja11xx.c567 phy_write_mmd(phydev, MDIO_MMD_VEND1, in tja1120_get_extts()
649 phy_write_mmd(phydev, MDIO_MMD_VEND1, in tja1120_get_hwtxts()
755 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_gpio_config()
828 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_or_falling()
1051 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_hwtstamp()
1056 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_hwtstamp()
1288 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_handle_interrupt()
1323 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_cable_test_start()
1432 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_ptp_init()
1840 phy_write_mmd(phydev, MDIO_MMD_VEND1, in tja1103_nmi_handler()
[all …]
H A Dmicrochip_t1.c1293 phy_modify_mmd(phydev, MDIO_MMD_VEND1, in lan887x_phy_init()
1314 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, in lan887x_phy_init()
1684 rc = phy_modify_mmd(phydev, MDIO_MMD_VEND1, in lan887x_cable_test_prep()
1727 return phy_write_mmd(phydev, MDIO_MMD_VEND1, in lan887x_cable_test_prep()
1752 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, in lan887x_cable_test_chk()
1762 return phy_write_mmd(phydev, MDIO_MMD_VEND1, in lan887x_cable_test_chk()
1933 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, in lan887x_cable_test_report()
1983 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, in lan887x_get_sqi_100M()
2019 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, in lan887x_get_sqi_100M()
2025 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, in lan887x_get_sqi_100M()
[all …]
H A Dadin.c278 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in adin_config_rgmii_mode()
314 return phy_write_mmd(phydev, MDIO_MMD_VEND1, in adin_config_rgmii_mode()
324 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in adin_config_rmii_mode()
341 return phy_write_mmd(phydev, MDIO_MMD_VEND1, in adin_config_rmii_mode()
456 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in adin_set_fast_down()
461 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in adin_set_fast_down()
612 if (devad == MDIO_MMD_VEND1) in adin_cl45_to_adin_reg()
780 rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in adin_soft_reset()
789 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, in adin_soft_reset()
931 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, in adin_cable_test_report_pair()
[all …]
H A Dmxl-gpy.c190 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_TEMP_STA); in gpy_hwmon_read()
259 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_ADDRLO, in gpy_mbox_read()
267 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_CMD, cmd); in gpy_mbox_read()
276 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, in gpy_mbox_read()
283 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_DATA); in gpy_mbox_read()
377 phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, in gpy_2500basex_chk()
386 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL); in gpy_sgmii_aneg_en()
504 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, in gpy_config_aneg()
551 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, in gpy_update_interface()
569 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, in gpy_update_interface()
[all …]
H A Dteranetics.c39 if (!phy_read_mmd(phydev, MDIO_MMD_VEND1, 93)) in teranetics_aneg_done()
54 if (!phy_read_mmd(phydev, MDIO_MMD_VEND1, 93)) { in teranetics_read_status()
H A Dadin1100.c198 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, in adin_set_powerdown_mode()
203 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ADIN_CRSM_STAT, ret, in adin_set_powerdown_mode()
236 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN_CRSM_SFT_RST, ADIN_CRSM_SFT_RST_EN); in adin_soft_reset()
240 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ADIN_CRSM_STAT, ret, in adin_soft_reset()
H A Dair_en8811h.c438 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, in en8811h_wait_mcu_ready()
871 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_1, in en8811h_config_init()
875 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_2, in en8811h_config_init()
879 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3, in en8811h_config_init()
883 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4, in en8811h_config_init()
1027 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3, in en8811h_clear_intr()
1032 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4, in en8811h_clear_intr()
H A Dbcm84881.c209 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, 0x4011); in bcm84881_read_status()
/linux-6.15/drivers/net/phy/mediatek/
H A Dmtk-ge-soc.c654 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
660 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
671 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
682 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
693 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
962 phy_modify_mmd(phydev, MDIO_MMD_VEND1, in mt798x_phy_eee()
969 phy_modify_mmd(phydev, MDIO_MMD_VEND1, in mt798x_phy_eee()
975 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in mt798x_phy_eee()
979 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in mt798x_phy_eee()
982 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in mt798x_phy_eee()
[all …]
H A Dmtk-ge.c49 phy_modify_mmd(phydev, MDIO_MMD_VEND1, in mtk_gephy_config_init()
59 phy_modify_mmd(phydev, MDIO_MMD_VEND1, in mtk_gephy_config_init()
82 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, in mt7531_phy_config_init()
87 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_GBE_MODE_TX_DELAY_SEL, in mt7531_phy_config_init()
91 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TEST_MODE_TX_DELAY_SEL, in mt7531_phy_config_init()
/linux-6.15/drivers/net/phy/aquantia/
H A Daquantia_firmware.c96 phy_write_mmd(phydev, MDIO_MMD_VEND1, in aqr_fw_load_memory()
99 phy_write_mmd(phydev, MDIO_MMD_VEND1, in aqr_fw_load_memory()
102 phy_write_mmd(phydev, MDIO_MMD_VEND1, in aqr_fw_load_memory()
116 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE5, in aqr_fw_load_memory()
118 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE6, in aqr_fw_load_memory()
121 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE1, in aqr_fw_load_memory()
138 up_crc = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE2); in aqr_fw_load_memory()
262 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL2, in aqr_fw_boot()
280 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_SC, in aqr_fw_boot()
284 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL2, in aqr_fw_boot()
[all …]
H A Daquantia_leds.c17 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_PROV(index), in aqr_phy_led_brightness_set()
55 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_PROV(index)); in aqr_phy_led_hw_control_get()
113 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_PROV(index), in aqr_phy_led_hw_control_set()
122 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_DRIVE(index), in aqr_phy_led_active_low_set()
H A Daquantia_hwmon.c44 int temp = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg); in aqr_hwmon_get()
65 return phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, (u16)temp); in aqr_hwmon_set()
70 int val = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg); in aqr_hwmon_test_bit()
H A Daquantia_main.c262 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK, in aqr_config_intr()
613 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg); in aqr107_read_rate()
758 false, phydev, MDIO_MMD_VEND1, in aqr_wait_reset_complete()
774 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID); in aqr107_chip_info()
781 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1); in aqr107_chip_info()
916 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9); in aqr107_link_change_notify()
936 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, in aqr107_wait_processor_intensive_op()
963 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, in aqr107_suspend()
975 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, in aqr107_resume()
1004 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, in aqr107_fill_interface_modes()
[all …]
/linux-6.15/drivers/net/ethernet/chelsio/cxgb3/
H A Daq100x.c71 int err = t3_phy_reset(phy, MDIO_MMD_VEND1, 3000); in aq100x_reset()
86 err = t3_mdio_write(phy, MDIO_MMD_VEND1, AQ_IMASK_GLOBAL, IMASK_GLOBAL); in aq100x_intr_enable()
92 return t3_mdio_write(phy, MDIO_MMD_VEND1, AQ_IMASK_GLOBAL, 0); in aq100x_intr_disable()
99 t3_mdio_read(phy, MDIO_MMD_VEND1, AQ_IFLAG_GLOBAL, &v); in aq100x_intr_clear()
110 err = t3_mdio_read(phy, MDIO_MMD_VEND1, AQ_IFLAG_GLOBAL, &cause); in aq100x_intr_handler()
292 err = t3_mdio_read(phy, MDIO_MMD_VEND1, MDIO_CTRL1, &v); in t3_aq100x_phy_prep()
319 t3_mdio_read(phy, MDIO_MMD_VEND1, AQ_FW_VERSION, &v); in t3_aq100x_phy_prep()
328 err = t3_mdio_read(phy, MDIO_MMD_VEND1, MDIO_CTRL1, &v); in t3_aq100x_phy_prep()
332 err = t3_mdio_change_bits(phy, MDIO_MMD_VEND1, MDIO_CTRL1, in t3_aq100x_phy_prep()
/linux-6.15/drivers/net/ethernet/aquantia/atlantic/macsec/
H A Dmacsec_api.c83 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in set_raw_ingress_record()
86 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in set_raw_ingress_record()
94 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in set_raw_ingress_record()
97 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in set_raw_ingress_record()
108 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in set_raw_ingress_record()
137 ret = aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in get_raw_ingress_record()
180 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in set_raw_egress_record()
183 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in set_raw_egress_record()
190 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in set_raw_egress_record()
192 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in set_raw_egress_record()
[all …]
/linux-6.15/drivers/net/dsa/mv88e6xxx/
H A Dpcs-639x.c680 { MDIO_MMD_VEND1, 0x8093, 0xcb5a, 0xffff }, in mv88e6393x_erratum_5_2()
681 { MDIO_MMD_VEND1, 0x8171, 0x7088, 0xffff }, in mv88e6393x_erratum_5_2()
682 { MDIO_MMD_VEND1, 0x80c9, 0x311a, 0xffff }, in mv88e6393x_erratum_5_2()
683 { MDIO_MMD_VEND1, 0x80a2, 0x8000, 0xff7f }, in mv88e6393x_erratum_5_2()
684 { MDIO_MMD_VEND1, 0x80a9, 0x0000, 0xfff0 }, in mv88e6393x_erratum_5_2()
685 { MDIO_MMD_VEND1, 0x80a3, 0x0000, 0xf8ff }, in mv88e6393x_erratum_5_2()
736 return mdiodev_c45_write(&mpcs->mdio, MDIO_MMD_VEND1, 0x8000, 0x58); in mv88e6393x_fix_2500basex_an()
/linux-6.15/drivers/net/ethernet/aquantia/atlantic/
H A Daq_phy.c165 val = aq_phy_read_reg(aq_hw, MDIO_MMD_VEND1, in aq_phy_disable_ptp()
168 aq_phy_write_reg(aq_hw, MDIO_MMD_VEND1, in aq_phy_disable_ptp()
/linux-6.15/drivers/net/phy/realtek/
H A Drealtek_main.c872 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0); in rtl822xb_config_init()
876 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1, in rtl822xb_config_init()
883 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503); in rtl822xb_config_init()
887 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455); in rtl822xb_config_init()
891 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020); in rtl822xb_config_init()
903 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION); in rtl822xb_get_rate_matching()
959 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3); in rtl822xb_update_interface()
/linux-6.15/include/uapi/linux/
H A Dmdio.h28 #define MDIO_MMD_VEND1 30 /* Vendor specific 1 */ macro
160 #define MDIO_DEVS_VEND1 MDIO_DEVS_PRESENT(MDIO_MMD_VEND1)
/linux-6.15/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_x550.c2341 MDIO_MMD_VEND1, in ixgbe_get_lasi_ext_t_x550em()
2349 MDIO_MMD_VEND1, in ixgbe_get_lasi_ext_t_x550em()
2358 MDIO_MMD_VEND1, in ixgbe_get_lasi_ext_t_x550em()
2374 MDIO_MMD_VEND1, in ixgbe_get_lasi_ext_t_x550em()
2455 MDIO_MMD_VEND1, in ixgbe_enable_lasi_ext_t_x550em()
2464 MDIO_MMD_VEND1, in ixgbe_enable_lasi_ext_t_x550em()
2471 MDIO_MMD_VEND1, in ixgbe_enable_lasi_ext_t_x550em()
2480 MDIO_MMD_VEND1, in ixgbe_enable_lasi_ext_t_x550em()
2487 MDIO_MMD_VEND1, in ixgbe_enable_lasi_ext_t_x550em()
3340 MDIO_MMD_VEND1, in ixgbe_init_ext_t_x550em()
[all …]
H A Dixgbe_phy.c1303 MDIO_MMD_VEND1, in ixgbe_check_phy_link_tnx()
2809 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, &reg); in ixgbe_set_copper_phy_power()
2821 status = hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, reg); in ixgbe_set_copper_phy_power()
/linux-6.15/drivers/net/ethernet/microchip/
H A Dlan743x_ethtool.c1217 { ETH_SR_VSMMD_DEV_ID1, MDIO_MMD_VEND1, 0x0002}, in lan743x_sgmii_regs()
1218 { ETH_SR_VSMMD_DEV_ID2, MDIO_MMD_VEND1, 0x0003}, in lan743x_sgmii_regs()
1219 { ETH_SR_VSMMD_PCS_ID1, MDIO_MMD_VEND1, 0x0004}, in lan743x_sgmii_regs()
1220 { ETH_SR_VSMMD_PCS_ID2, MDIO_MMD_VEND1, 0x0005}, in lan743x_sgmii_regs()
1221 { ETH_SR_VSMMD_STS, MDIO_MMD_VEND1, 0x0008}, in lan743x_sgmii_regs()
1222 { ETH_SR_VSMMD_CTRL, MDIO_MMD_VEND1, 0x0009}, in lan743x_sgmii_regs()
/linux-6.15/rust/kernel/net/phy/
H A Dreg.rs171 pub const VEND1: Self = Mmd(uapi::MDIO_MMD_VEND1 as u8);
/linux-6.15/drivers/net/dsa/sja1105/
H A Dsja1105_mdio.c20 if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2) in sja1105_pcs_mdio_read_c45()
46 if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2) in sja1105_pcs_mdio_write_c45()

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