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Searched refs:MDIO_MMD_AN (Results 1 – 25 of 39) sorted by relevance

12

/linux-6.15/drivers/net/phy/
H A Dphy-c45.c327 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, in genphy_c45_an_disable_aneg()
347 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg, in genphy_c45_restart_aneg()
371 ret = phy_read_mmd(phydev, MDIO_MMD_AN, reg); in genphy_c45_check_and_restart_aneg()
405 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); in genphy_c45_aneg_done()
426 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); in genphy_c45_read_link()
530 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in genphy_c45_read_lpa()
549 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA); in genphy_c45_read_lpa()
695 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, in genphy_c45_write_eee_adv()
713 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, in genphy_c45_write_eee_adv()
729 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, in genphy_c45_write_eee_adv()
[all …]
H A Dbcm84881.c113 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, in bcm84881_config_aneg()
129 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in bcm84881_aneg_done()
133 bmsr = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_C22 + MII_BMSR); in bcm84881_aneg_done()
146 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); in bcm84881_read_status()
155 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in bcm84881_read_status()
159 bmsr = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_C22 + MII_BMSR); in bcm84881_read_status()
185 val = phy_read_mmd(phydev, MDIO_MMD_AN, in bcm84881_read_status()
H A Dmarvell-88q2xxx.c142 { MDIO_MMD_AN, 0x8032, 0x0064 },
143 { MDIO_MMD_AN, 0x8031, 0x0a01 },
144 { MDIO_MMD_AN, 0x8031, 0x0c01 },
150 { MDIO_MMD_AN, MDIO_AN_T1_CTRL, 0x0 },
168 { MDIO_MMD_AN, 0x8032, 0x2020 },
169 { MDIO_MMD_AN, 0x8031, 0xa28 },
170 { MDIO_MMD_AN, 0x8031, 0xc28 },
180 { MDIO_MMD_AN, MDIO_AN_T1_CTRL, 0x0 },
210 { MDIO_MMD_AN, 0x8032, 0x2020 },
211 { MDIO_MMD_AN, 0x8031, 0xa28 },
[all …]
H A Dadin1100.c84 ret = phy_read_mmd(phydev, MDIO_MMD_AN, ADIN_AN_PHY_INST_STATUS); in adin_read_status()
117 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN); in adin_config_aneg()
120 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN); in adin_config_aneg()
126 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H, in adin_config_aneg()
135 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H, in adin_config_aneg()
H A Dteranetics.c62 reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in teranetics_read_status()
H A Dbcm-phy-lib.c377 val = phy_read_mmd(phydev, MDIO_MMD_AN, BRCM_CL45VEN_EEE_CONTROL); in bcm_phy_set_eee()
386 phy_write_mmd(phydev, MDIO_MMD_AN, BRCM_CL45VEN_EEE_CONTROL, (u32)val); in bcm_phy_set_eee()
389 val = phy_read_mmd(phydev, MDIO_MMD_AN, BCM_CL45VEN_EEE_ADV); in bcm_phy_set_eee()
405 phy_write_mmd(phydev, MDIO_MMD_AN, BCM_CL45VEN_EEE_ADV, (u32)val); in bcm_phy_set_eee()
512 { "phy_lpi_count", MDIO_MMD_AN, BRCM_CL45VEN_EEE_LPI_CNT, 0, 16 },
H A Dmarvell10g.c612 err = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2, in mv2110_set_mactype()
618 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_AN, in mv2110_set_mactype()
626 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2, in mv2110_set_mactype()
937 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000, in mv3310_config_aneg()
1024 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in mv3310_read_status_copper()
1081 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000); in mv3310_read_status_copper()
/linux-6.15/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-mdio.c184 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0); in xgbe_an73_clear_interrupts()
189 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0); in xgbe_an73_disable_interrupts()
407 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1); in xgbe_an73_set()
416 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg); in xgbe_an73_set()
532 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0); in xgbe_an73_tx_xnp()
533 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0); in xgbe_an73_tx_xnp()
534 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP, msg); in xgbe_an73_tx_xnp()
555 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); in xgbe_an73_rx_bpa()
569 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_XNP); in xgbe_an73_rx_xnp()
1570 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1)); in xgbe_dump_phy_registers()
[all …]
H A Dxgbe-phy-v1.c243 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); in xgbe_phy_an_outcome()
244 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); in xgbe_phy_an_outcome()
267 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); in xgbe_phy_an_outcome()
268 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); in xgbe_phy_an_outcome()
291 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); in xgbe_phy_an_outcome()
292 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); in xgbe_phy_an_outcome()
H A Dxgbe-phy-v2.c1692 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); in xgbe_phy_an73_redrv_outcome()
1693 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); in xgbe_phy_an73_redrv_outcome()
1755 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); in xgbe_phy_an73_redrv_outcome()
1756 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); in xgbe_phy_an73_redrv_outcome()
1773 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); in xgbe_phy_an73_outcome()
1774 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); in xgbe_phy_an73_outcome()
1797 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); in xgbe_phy_an73_outcome()
1798 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); in xgbe_phy_an73_outcome()
1813 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); in xgbe_phy_an73_outcome()
1814 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); in xgbe_phy_an73_outcome()
/linux-6.15/drivers/vfio/platform/reset/
H A Dvfio_platform_amdxgbe.c85 value = xmdio_read(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_CTRL1); in vfio_platform_amdxgbe_reset()
87 xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_CTRL1, value); in vfio_platform_amdxgbe_reset()
90 xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_AN_INTMASK, 0); in vfio_platform_amdxgbe_reset()
93 xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_AN_INT, 0); in vfio_platform_amdxgbe_reset()
/linux-6.15/drivers/net/ethernet/chelsio/cxgb3/
H A Daq100x.c134 MDIO_MMD_AN, MDIO_CTRL1, in aq100x_autoneg_enable()
147 MDIO_MMD_AN, MDIO_CTRL1, in aq100x_autoneg_restart()
162 err = t3_mdio_change_bits(phy, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, in aq100x_advertise()
173 err = t3_mdio_change_bits(phy, MDIO_MMD_AN, AQ_1G_CTRL, in aq100x_advertise()
188 err = t3_mdio_change_bits(phy, MDIO_MMD_AN, MDIO_AN_ADVERTISE, in aq100x_advertise()
223 err = t3_mdio_read(phy, MDIO_MMD_AN, AQ_ANEG_STAT, &v); in aq100x_get_link_status()
/linux-6.15/drivers/net/phy/aquantia/
H A Daquantia_main.c287 irq_status = phy_read_mmd(phydev, MDIO_MMD_AN, in aqr_handle_interrupt()
307 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); in aqr_read_status()
394 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, adv); in aqr105_setup_forced()
405 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, in aqr105_setup_forced()
472 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1); in aqr105_read_rate()
574 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1); in aqr107_read_rate()
691 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV); in aqr107_get_downshift()
715 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, in aqr107_set_downshift()
889 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); in aqr107_link_change_notify()
897 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4); in aqr107_link_change_notify()
[all …]
/linux-6.15/drivers/net/phy/qcom/
H A Dqca808x.c107 phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1, in qca808x_phy_fast_retrain_config()
163 ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE); in qca808x_is_1g_only()
204 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, in qca808x_config_init()
257 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); in qca808x_read_status()
400 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, in qca808x_config_aneg()
492 return phy_modify_mmd(phydev, MDIO_MMD_AN, reg, in qca808x_led_hw_control_set()
523 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); in qca808x_led_hw_control_get()
553 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, in qca808x_led_hw_control_reset()
619 return phy_modify_mmd(phydev, MDIO_MMD_AN, in qca808x_led_polarity_set()
H A Dqca807x.c233 return phy_modify_mmd(phydev, MDIO_MMD_AN, reg, mask, in qca807x_led_hw_control_set()
265 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); in qca807x_led_hw_control_get()
284 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); in qca807x_led_hw_control_get()
326 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, mask); in qca807x_led_hw_control_reset()
375 val = phy_read_mmd(priv->phy, MDIO_MMD_AN, reg); in qca807x_gpio_get()
388 val = phy_read_mmd(priv->phy, MDIO_MMD_AN, reg); in qca807x_gpio_set()
393 phy_write_mmd(priv->phy, MDIO_MMD_AN, reg, val); in qca807x_gpio_set()
667 MDIO_MMD_AN, in qca807x_sfp_insert()
770 control_dac = phy_read_mmd(phydev, MDIO_MMD_AN, in qca807x_config_init()
779 return phy_write_mmd(phydev, MDIO_MMD_AN, in qca807x_config_init()
H A Dqcom-phy-lib.c626 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, in qca808x_led_reg_hw_control_enable()
635 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); in qca808x_led_reg_hw_control_status()
643 return phy_modify_mmd(phydev, MDIO_MMD_AN, reg, in qca808x_led_reg_brightness_set()
657 ret = phy_modify_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_LED_GLOBAL, in qca808x_led_reg_blink_set()
664 ret = phy_modify_mmd(phydev, MDIO_MMD_AN, reg, in qca808x_led_reg_blink_set()
/linux-6.15/drivers/net/ethernet/sfc/falcon/
H A Dmdio_10g.c55 if (mmd != MDIO_MMD_AN) { in ef4_mdio_check_mmd()
285 ef4_mdio_write(efx, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg); in ef4_mdio_an_reconfigure()
291 reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_CTRL1); in ef4_mdio_an_reconfigure()
293 ef4_mdio_write(efx, MDIO_MMD_AN, MDIO_CTRL1, reg); in ef4_mdio_an_reconfigure()
307 ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_LPA)); in ef4_mdio_get_pause()
H A Dtenxpress.c263 reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_STAT1); in sfx7101_check_bad_lp()
446 reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL); in tenxpress_get_link_ksettings()
449 reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); in tenxpress_get_link_ksettings()
473 ef4_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, in sfx7101_set_npage_adv()
/linux-6.15/drivers/net/
H A Dmdio.c142 mdio_set_flag(mdio, mdio->prtad, MDIO_MMD_AN, MDIO_CTRL1, in mdio45_nway_restart()
153 reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_AN, addr); in mdio45_get_an()
258 reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_AN, in mdio45_ethtool_ksettings_get_npage()
276 MDIO_MMD_AN, MDIO_STAT1); in mdio45_ethtool_ksettings_get_npage()
402 devad = MDIO_MMD_AN; in mdio_mii_ioctl()
/linux-6.15/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_phy.c1118 MDIO_MMD_AN, &autoneg_reg); in ixgbe_setup_phy_link_generic()
1142 MDIO_MMD_AN, autoneg_reg); in ixgbe_setup_phy_link_generic()
1160 MDIO_MMD_AN, &autoneg_reg); in ixgbe_setup_phy_link_generic()
1165 MDIO_MMD_AN, autoneg_reg); in ixgbe_setup_phy_link_generic()
1341 MDIO_MMD_AN, in ixgbe_setup_phy_link_tnx()
1349 MDIO_MMD_AN, in ixgbe_setup_phy_link_tnx()
1356 MDIO_MMD_AN, in ixgbe_setup_phy_link_tnx()
1364 MDIO_MMD_AN, in ixgbe_setup_phy_link_tnx()
1371 MDIO_MMD_AN, in ixgbe_setup_phy_link_tnx()
1380 MDIO_MMD_AN, in ixgbe_setup_phy_link_tnx()
[all …]
H A Dixgbe_x550.c2390 MDIO_MMD_AN, &reg); in ixgbe_get_lasi_ext_t_x550em()
2397 MDIO_MMD_AN, &reg); in ixgbe_get_lasi_ext_t_x550em()
2440 MDIO_MMD_AN, &reg); in ixgbe_enable_lasi_ext_t_x550em()
2448 MDIO_MMD_AN, reg); in ixgbe_enable_lasi_ext_t_x550em()
2615 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, in ixgbe_ext_phy_t_x550em_get_link()
2667 MDIO_MMD_AN, in ixgbe_setup_internal_phy_t_x550em()
2831 MDIO_MMD_AN, in ixgbe_get_lcd_t_x550em()
3067 MDIO_MMD_AN, in ixgbe_enter_lplu_t_x550em()
3089 MDIO_MMD_AN, in ixgbe_enter_lplu_t_x550em()
3095 MDIO_MMD_AN, in ixgbe_enter_lplu_t_x550em()
[all …]
/linux-6.15/drivers/net/pcs/
H A Dpcs-xpcs.c381 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV3, adv); in _xpcs_config_aneg_c73()
394 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV2, adv); in _xpcs_config_aneg_c73()
405 return xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV1, adv); in _xpcs_config_aneg_c73()
417 return xpcs_modify(xpcs, MDIO_MMD_AN, MDIO_CTRL1, in xpcs_config_aneg_c73()
429 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA); in xpcs_aneg_done_c73()
460 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA + i); in xpcs_read_lpa_c73()
927 an_stat1 = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1); in xpcs_get_state_c73()
/linux-6.15/include/uapi/linux/
H A Dmdio.h25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */ macro
158 #define MDIO_DEVS_AN MDIO_DEVS_PRESENT(MDIO_MMD_AN)
/linux-6.15/drivers/net/phy/realtek/
H A Drealtek_main.c772 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) in rtlgen_read_mmd()
774 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) in rtlgen_read_mmd()
789 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) in rtlgen_write_mmd()
806 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) in rtl822x_read_mmd()
808 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) in rtl822x_read_mmd()
822 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) in rtl822x_write_mmd()
/linux-6.15/rust/kernel/net/phy/
H A Dreg.rs155 pub const AN: Self = Mmd(uapi::MDIO_MMD_AN as u8);

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