Searched refs:MACRO_TILE_ASPECT (Results 1 – 16 of 16) sorted by relevance
97 #define MACRO_TILE_ASPECT(x) ((x) << 18) macro425 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v6_0_tiling_mode_table_init()433 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v6_0_tiling_mode_table_init()441 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v6_0_tiling_mode_table_init()448 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | in gfx_v6_0_tiling_mode_table_init()650 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); in gfx_v6_0_tiling_mode_table_init()658 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); in gfx_v6_0_tiling_mode_table_init()666 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); in gfx_v6_0_tiling_mode_table_init()674 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); in gfx_v6_0_tiling_mode_table_init()682 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); in gfx_v6_0_tiling_mode_table_init()[all …]
2209 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v8_0_tiling_mode_table_init()2213 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v8_0_tiling_mode_table_init()2217 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v8_0_tiling_mode_table_init()2221 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v8_0_tiling_mode_table_init()2225 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v8_0_tiling_mode_table_init()2229 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v8_0_tiling_mode_table_init()2233 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v8_0_tiling_mode_table_init()2237 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v8_0_tiling_mode_table_init()2241 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v8_0_tiling_mode_table_init()2401 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v8_0_tiling_mode_table_init()[all …]
1127 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v7_0_tiling_mode_table_init()1131 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v7_0_tiling_mode_table_init()1135 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v7_0_tiling_mode_table_init()1139 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v7_0_tiling_mode_table_init()1143 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v7_0_tiling_mode_table_init()1147 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v7_0_tiling_mode_table_init()1151 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | in gfx_v7_0_tiling_mode_table_init()1155 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v7_0_tiling_mode_table_init()1159 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v7_0_tiling_mode_table_init()1163 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v7_0_tiling_mode_table_init()[all …]
205 # define MACRO_TILE_ASPECT(x) ((x) << 4) macro
1930 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v8_0_crtc_do_set_base()
2012 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v6_0_crtc_do_set_base()
1991 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v10_0_crtc_do_set_base()
2041 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v11_0_crtc_do_set_base()
2503 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); in si_tiling_mode_table_init()2512 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); in si_tiling_mode_table_init()2521 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); in si_tiling_mode_table_init()2530 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); in si_tiling_mode_table_init()2539 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); in si_tiling_mode_table_init()2548 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); in si_tiling_mode_table_init()2557 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); in si_tiling_mode_table_init()2566 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); in si_tiling_mode_table_init()2575 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); in si_tiling_mode_table_init()2584 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); in si_tiling_mode_table_init()[all …]
2581 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in cik_tiling_mode_table_init()2585 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in cik_tiling_mode_table_init()2589 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in cik_tiling_mode_table_init()2593 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in cik_tiling_mode_table_init()2597 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | in cik_tiling_mode_table_init()2601 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | in cik_tiling_mode_table_init()2605 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | in cik_tiling_mode_table_init()2609 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in cik_tiling_mode_table_init()2613 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in cik_tiling_mode_table_init()2617 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in cik_tiling_mode_table_init()[all …]
1216 # define MACRO_TILE_ASPECT(x) ((x) << 18) macro
1270 # define MACRO_TILE_ASPECT(x) ((x) << 4) macro
2416 # define MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6) macro
2374 MACRO_TILE_ASPECT(mtaspect) | in evergreen_packet3_check()
189 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
1766 typedef enum MACRO_TILE_ASPECT { enum1771 } MACRO_TILE_ASPECT; typedef