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/linux-6.15/Documentation/devicetree/bindings/display/bridge/
H A Drenesas,lvds.yaml7 title: Renesas R-Car LVDS Encoder
19 - renesas,r8a7742-lvds # for RZ/G1H compatible LVDS encoders
20 - renesas,r8a7743-lvds # for RZ/G1M compatible LVDS encoders
21 - renesas,r8a7744-lvds # for RZ/G1N compatible LVDS encoders
22 - renesas,r8a774a1-lvds # for RZ/G2M compatible LVDS encoders
23 - renesas,r8a774b1-lvds # for RZ/G2N compatible LVDS encoders
24 - renesas,r8a774c0-lvds # for RZ/G2E compatible LVDS encoders
25 - renesas,r8a774e1-lvds # for RZ/G2H compatible LVDS encoders
26 - renesas,r8a7790-lvds # for R-Car H2 compatible LVDS encoders
62 description: LVDS output port
[all …]
H A Dlvds-codec.yaml7 title: Transparent LVDS encoders and decoders
13 This binding supports transparent LVDS encoders and decoders that don't
18 to LVDS panels. This binding targets devices compatible with the following
23 [LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National
42 - ti,ds90cf364a # For the DS90CF364A FPD-Link LVDS Receiver
45 - ti,sn65lvds94 # For the SN65DS94 LVDS serdes
48 - thine,thc63lvdm83d # For the THC63LVDM83D LVDS serializer
58 For LVDS encoders, port 0 is the parallel input
59 For LVDS decoders, port 0 is the LVDS input
79 For LVDS encoders, port 1 is the LVDS output
[all …]
H A Dlontium,lt9211.yaml7 title: Lontium LT9211 DSI/LVDS/DPI to DSI/LVDS/DPI bridge.
13 The LT9211 are bridge devices which convert Single/Dual-Link DSI/LVDS
14 or Single DPI to Single/Dual-Link DSI/LVDS or Single DPI.
42 LVDS port-1 for LVDS input or DPI input.
47 Additional MIPI port-2 for MIPI input or LVDS port-2
48 for LVDS input. Used in combination with primary
55 LVDS port-1 for LVDS output or DPI output.
60 Additional MIPI port-2 for MIPI output or LVDS port-2
61 for LVDS output. Used in combination with primary
H A Dtoshiba,tc358775.yaml7 title: Toshiba TC358775 DSI to LVDS bridge
13 This binding supports DSI to LVDS bridges TC358765 and TC358775
17 Up to 1600x1200 24-bit/pixel resolution for single-link LVDS display panel
18 limited by 135 MHz LVDS speed
19 Up to WUXGA (1920x1200 24-bit pixels) resolution for dual-link LVDS display
20 panel, limited by 270 MHz LVDS speed.
33 description: 1.2V LVDS Power Supply
75 Video port for LVDS output (panel or connector).
80 Video port for Dual link LVDS output (panel or connector).
110 /* For single-link LVDS display panel */
[all …]
H A Dite,it6263.yaml7 title: ITE IT6263 LVDS to HDMI converter
13 The IT6263 is a high-performance single-chip De-SSC(De-Spread Spectrum) LVDS
14 to HDMI converter. Combined with LVDS receiver and HDMI 1.4a transmitter,
15 the IT6263 supports LVDS input and HDMI 1.4 output by conversion function.
16 The built-in LVDS receiver can support single-link and dual-link LVDS inputs,
76 description: 3.3V LVDS frontend power
79 description: 1.8V LVDS frontend analog power
82 description: 1.8V LVDS frontend PLL power
151 /* single-link LVDS input */
197 /* dual-link LVDS input */
H A Dthine,thc63lvd1024.yaml7 title: Thine Electronics THC63LVD1024 LVDS Decoder
14 The THC63LVD1024 is a dual link LVDS receiver designed to convert LVDS
16 modes, handling up to two LVDS input streams and up to two digital CMOS/TTL
45 description: First LVDS input port
49 description: Second LVDS input port
73 Power supply for the TTL output, TTL CLOCKOUT signal, LVDS input, PLL and
H A Dti,sn65dsi83.yaml7 title: SN65DSI83 and SN65DSI84 DSI to LVDS bridge chip
14 to 1x Single-link LVDS
17 to 1x Dual-link or 2x Single-link LVDS
86 description: Video port for LVDS Channel-A output (panel or bridge).
90 description: Video port for LVDS Channel-B output (panel or bridge).
119 description: LVDS diferential output voltage <min max> for clock
126 description: LVDS diferential output voltage <min max> for data
H A Dfsl,ldb.yaml7 title: Freescale i.MX8MP DPI to LVDS bridge chip
14 for configuring the on-SoC DPI-to-LVDS serializer. This describes
48 description: Video port for LVDS Channel-A output (panel or bridge).
52 description: Video port for LVDS Channel-B output (panel or bridge).
/linux-6.15/Documentation/devicetree/bindings/display/
H A Dlvds-dual-ports.yaml7 title: Dual-link LVDS Display Common Properties
13 Common properties for LVDS displays with dual LVDS links. Extend LVDS display
16 Dual-link LVDS displays receive odd pixels and even pixels separately from
17 the dual LVDS links. One link receives odd pixels and the other receives
18 even pixels. Some of those displays may also use only one LVDS link to
33 port@0 represents the first LVDS input link.
34 port@1 represents the second LVDS input link.
39 description: LVDS input link for odd pixels
43 description: LVDS input link for even pixels
H A Dst,stm32mp25-lvds.yaml7 title: STMicroelectronics STM32 LVDS Display Interface Transmitter
14 The STMicroelectronics STM32 LVDS Display Interface Transmitter handles the
15 LVDS protocol: it maps the pixels received from the upstream Pixel-DMA (LTDC)
16 onto the LVDS PHY.
19 - LVDS host: handles the LVDS protocol (FPD / OpenLDI) and maps its input
21 - LVDS PHY: parallelize the data and drives the LVDS data lanes
22 - LVDS wrapper: handles top-level settings
24 The LVDS controller driver supports the following high-level features:
39 Provides the internal LVDS PHY clock to the framework.
64 LVDS input port node, connected to the LTDC RGB output port.
[all …]
H A Dlvds-data-mapping.yaml7 title: LVDS Data Mapping
14 LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple
16 to LVDS devices. This bindings supports devices compatible with the following
21 [LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National
43 LVDS data mappings are defined as follows.
46 [VESA] specifications. Data are transferred as follows on 3 LVDS lanes.
57 specifications. Data are transferred as follows on 4 LVDS lanes.
69 are transferred as follows on 5 LVDS lanes.
82 Data are transferred as follows on 4 LVDS lanes.
94 transferred as follows on 5 LVDS lanes.
/linux-6.15/Documentation/devicetree/bindings/phy/
H A Dfsl,imx8qm-lvds-phy.yaml7 title: Mixel LVDS PHY for Freescale i.MX8qm SoC
13 The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC.
15 groups of four data lanes of LVDS data streams. A phase-locked
17 data streams over a fifth LVDS link. Every cycle of the transmit
19 through the two groups of LVDS data streams. Together with the
20 transmit clocks, the two groups of LVDS data streams form two
21 LVDS channels.
23 The Mixel LVDS PHY found on Freescale i.MX8qm SoC is controlled
36 Cell allows setting the LVDS channel index of the PHY.
37 Index 0 is for LVDS channel0 and index 1 is for LVDS channel1.
/linux-6.15/Documentation/devicetree/bindings/display/imx/
H A Dldb.txt1 Device-Tree bindings for LVDS Display Bridge (ldb)
3 LVDS Display Bridge
7 nodes describing each of the two LVDS encoder channels of the bridge.
15 interfaces as input for each LVDS channel.
23 "di0_pll" - LDB LVDS channel 0 mux
24 "di1_pll" - LDB LVDS channel 1 mux
25 "di0" - LDB LVDS channel 0 gate
26 "di1" - LDB LVDS channel 1 gate
44 LVDS Channel
59 to the four LVDS multiplexer inputs.
[all …]
/linux-6.15/Documentation/devicetree/bindings/display/panel/
H A Dpanel-lvds.yaml7 title: Generic LVDS Display Panel
42 # Admatec 9904379 10.1" 1024x600 LVDS panel
45 # AUO G084SN05 V9 8.4" 800x600 LVDS panel
47 # Chunghwa Picture Tubes Ltd. 7" WXGA (800x1280) TFT LCD LVDS panel
49 # EDT ETML0700Z9NDHA 7.0" WSVGA (1024x600) color TFT LCD LVDS panel
51 # HannStar Display Corp. HSD101PWW2 10.1" WXGA (1280x800) LVDS panel
53 # Hydis Technologies 7" WXGA (800x1280) TFT LCD LVDS panel
55 # Jenson Display BL-JT60050-01A 7" WSVGA (1024x600) color TFT LCD LVDS panel
H A Dpanel-simple-lvds-dual-ports.yaml7 title: Simple LVDS panels with one power supply and dual LVDS ports
15 This binding file is a collection of the LVDS panels that
16 has dual LVDS ports and requires only a single power-supply.
43 # BOE AV123Z7M-N17 12.3" (1920x720) LVDS TFT LCD panel
45 # Kaohsiung Opto-Electronics Inc. 10.1" WUXGA (1920 x 1200) LVDS TFT LCD panel
53 # NLT Technologies, Ltd. 15.6" FHD (1920x1080) LVDS TFT LCD panel
H A Dpanel-simple.yaml66 # BOE AV101HDT-a10 10.1" 1280x720 LVDS panel
68 # BOE BP082WX1-100 8.2" WXGA (1280x800) LVDS panel
70 # BOE BP101WX1-100 10.1" WXGA (1280x800) LVDS panel
128 # Emerging Display Technology Corp. LVDS WSVGA TFT Display with capacitive touch
153 # HannStar Display Corp. HSD100PXN1 10.1" XGA LVDS panel
169 # Innolux Corporation 10.1" G101ICE-L01 WXGA (1280x800) LVDS panel
185 # Kaohsiung Opto-Electronics. TX31D200VM0BAA 12.3" HSXGA LVDS panel
205 # Microchip AC69T88A 5" 800X480 LVDS interface TFT LCD Panel
221 # NEC LCD Technologies, Ltd. 12.1" WXGA (1280x800) LVDS TFT LCD panel
289 # Tianma Micro-electronics TM070JDHG34-00 7.0" WXGA (1280x800) LVDS TFT LCD panel
[all …]
/linux-6.15/drivers/gpu/drm/bridge/
H A DKconfig103 tristate "ITE IT6263 LVDS/HDMI bridge"
111 ITE IT6263 LVDS to HDMI bridge chip driver.
210 GE B850v3 that convert dual channel LVDS
219 Support for Microchip's LVDS serializer.
239 tristate "NXP PTN3460 DP/LVDS bridge"
244 NXP PTN3460 eDP-LVDS bridge chip driver.
247 tristate "Parade eDP/LVDS bridge"
253 Parade eDP-LVDS bridge chip driver.
334 tristate "TC358764 DSI/LVDS bridge"
340 Toshiba TC358764 DSI/LVDS bridge driver.
[all …]
/linux-6.15/drivers/gpu/drm/stm/
H A DKconfig27 tristate "STMicroelectronics LVDS Display Interface Transmitter DRM driver"
30 Enable support for LVDS encoders on STMicroelectronics SoC.
31 The STM LVDS is a bridge which serialize pixel stream onto
32 a LVDS protocol.
/linux-6.15/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull-colibri-wifi-iris-v2.dts31 /* This turns the LVDS transceiver on */
42 * This switches the LVDS transceiver to the single-channel
53 * This switches the LVDS transceiver to the 24-bit RGB mode.
65 * This switches the LVDS transceiver to VESA color mapping mode.
H A Dimx7d-colibri-iris-v2.dts31 * This switches the LVDS transceiver to VESA color mapping mode.
43 * This switches the LVDS transceiver to the 24-bit RGB mode.
53 * This switches the LVDS transceiver to the single-channel
63 /* This turns the LVDS transceiver on */
H A Dimx7s-colibri-iris-v2.dts31 * This switches the LVDS transceiver to VESA color mapping mode.
43 * This switches the LVDS transceiver to the 24-bit RGB mode.
53 * This switches the LVDS transceiver to the single-channel
63 /* This turns the LVDS transceiver on */
H A Dimx6ull-colibri-iris-v2.dts31 /* This turns the LVDS transceiver on */
42 * This switches the LVDS transceiver to the single-channel
53 * This switches the LVDS transceiver to the 24-bit RGB mode.
65 * This switches the LVDS transceiver to VESA color mapping mode.
/linux-6.15/arch/arm64/boot/dts/renesas/
H A Dr8a774c0-ek874-idk-2121wr.dts4 * connected to an Advantech IDK-2121WR 21.5" LVDS panel
68 * When GP0_17 is low LVDS[01] are connected to the LVDS connector
69 * When GP0_17 is high LVDS[01] are connected to the LT8918L
H A Dhihope-rzg2-ex-lvds.dtsi3 * Device Tree Source for the RZ/G2[MN] HiHope sub board LVDS common parts
20 * When GP1_20 is LOW LVDS0 is connected to the LVDS connector
/linux-6.15/drivers/gpu/drm/bridge/imx/
H A DKconfig35 tristate "Freescale i.MX8QM LVDS display bridge"
41 Choose this to enable the internal LVDS Display Bridge(LDB) found in
45 tristate "Freescale i.MX8QXP LVDS display bridge"
51 Choose this to enable the internal LVDS Display Bridge(LDB) found in

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