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Searched refs:LSC_CHICKEN_BIT_0_UDW (Results 1 – 4 of 4) sorted by relevance

/linux-6.15/drivers/gpu/drm/xe/
H A Dxe_wa.c352 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW,
367 XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW,
384 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3))
389 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8))
469 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
492 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
525 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
549 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
/linux-6.15/drivers/gpu/drm/i915/gt/
H A Dintel_workarounds.c2830 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, in general_render_compute_wa_init()
2852 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); in general_render_compute_wa_init()
2855 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3); in general_render_compute_wa_init()
2863 wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, in general_render_compute_wa_init()
H A Dintel_gt_regs.h1184 #define LSC_CHICKEN_BIT_0_UDW MCR_REG(0xe7c8 + 4) macro
/linux-6.15/drivers/gpu/drm/xe/regs/
H A Dxe_gt_regs.h522 #define LSC_CHICKEN_BIT_0_UDW XE_REG_MCR(0xe7c8 + 4) macro