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/linux-6.15/Documentation/devicetree/bindings/mfd/
H A Daspeed-lpc.yaml8 title: Aspeed Low Pin Count (LPC) Bus Controller
15 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
17 primary use case of the Aspeed LPC controller is as a slave on the bus
21 The LPC controller is represented as a multi-function device to account for the
26 * An LPC Host Interface Controller manages functions exposed to the host such
27 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
34 Additionally the state of the LPC controller influences the pinmux
66 LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART management
127 bytes written by the Host to the targeted LPC I/O pots.
145 description: The LPC I/O ports to snoop
[all …]
/linux-6.15/Documentation/translations/zh_TW/arch/loongarch/
H A Dirq-chip-model.rst16 斷控制器）、PCH-LPC（LS7A芯片組的LPC中斷控制器）和PCH-MSI（MSI中斷控制器）。
19 全局中斷控制器（每個芯片一個，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
28 PCH-LPC/PCH-MSI，然後被HTVECINTC統一收集，再發送到LIOINTC，最後到達CPUINTC::
51 | PCH-LPC | | Devices | | Devices |
64 PCH-LPC/PCH-MSI，然後被EIOINTC統一收集，再直接到達CPUINTC::
82 | PCH-LPC | | Devices | | Devices |
129 PCH-LPC::
157 - PCH-LPC：即《龍芯7A1000橋片用戶手冊》第24.3節所描述的“LPC中斷”。
/linux-6.15/Documentation/translations/zh_CN/arch/loongarch/
H A Dirq-chip-model.rst16 断控制器）、PCH-LPC（LS7A芯片组的LPC中断控制器）和PCH-MSI（MSI中断控制器）。
19 全局中断控制器（每个芯片一个，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
28 PCH-LPC/PCH-MSI，然后被HTVECINTC统一收集，再发送到LIOINTC，最后到达CPUINTC::
51 | PCH-LPC | | Devices | | Devices |
64 PCH-LPC/PCH-MSI，然后被EIOINTC统一收集，再直接到达CPUINTC::
82 | PCH-LPC | | Devices | | Devices |
150 送达CPUINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/PCH-LPC，然后由EIOINTC
169 | Devices | | PCH-LPC | | Devices |
216 PCH-LPC::
244 - PCH-LPC：即《龙芯7A1000桥片用户手册》第24.3节所描述的“LPC中断”。
/linux-6.15/Documentation/devicetree/bindings/timer/
H A Dst,stih407-lpc1 STMicroelectronics Low Power Controller (LPC) - Clocksource
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
13 - reg : LPC registers base address + size
14 - interrupts : LPC interrupt line number and associated flags
15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
16 - st,lpc-mode : The LPC can run either one of three modes:
/linux-6.15/Documentation/devicetree/bindings/rtc/
H A Drtc-st-lpc.txt1 STMicroelectronics Low Power Controller (LPC) - RTC
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
13 - reg : LPC registers base address + size
14 - interrupts : LPC interrupt line number and associated flags
15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
16 - st,lpc-mode : The LPC can run either one of three modes:
/linux-6.15/Documentation/devicetree/bindings/watchdog/
H A Dst_lpc_wdt.txt1 STMicroelectronics Low Power Controller (LPC) - Watchdog
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
13 - reg : LPC registers base address + size
14 - interrupts : LPC interrupt line number and associated flags
15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
16 - st,lpc-mode : The LPC can run either one of three modes:
/linux-6.15/drivers/soc/aspeed/
H A DKconfig8 tristate "ASPEED LPC firmware cycle control"
13 Control LPC firmware cycle mappings through ioctl()s. The driver
15 host LPC read/write region can be buffered.
18 tristate "ASPEED LPC snoop support"
23 Provides a driver to control the LPC snoop interface which
25 the host to an arbitrary LPC I/O port.
/linux-6.15/Documentation/arch/loongarch/
H A Dirq-chip-model.rst11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
15 controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
24 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
48 | PCH-LPC | | Devices | | Devices |
61 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
80 | PCH-LPC | | Devices | | Devices |
158 go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and then go to CPUINTC directly::
176 | Devices | | PCH-LPC | | Devices |
223 PCH-LPC::
255 - PCH-LPC is "LPC Interrupts" described in Section 24.3 of
/linux-6.15/Documentation/ABI/stable/
H A Dsysfs-driver-aspeed-vuart5 will appear on the host <-> BMC LPC bus.
13 the UART will appear on the host <-> BMC LPC bus.
21 host via the BMC LPC bus.
/linux-6.15/Documentation/devicetree/bindings/ipmi/
H A Daspeed,ast2400-kcs-bmc.yaml14 interfaces on the LPC bus for in-band IPMI communication with their host.
48 The host CPU LPC IO data and status addresses for the device. For most
57 A 2-cell property expressing the LPC SerIRQ number and the interrupt
67 description: The LPC channel number in the controller
/linux-6.15/drivers/net/ethernet/nxp/
H A DKconfig3 tristate "NXP ethernet MAC on LPC devices"
9 some NXP LPC devices. You can safely enable this option for LPC32xx
/linux-6.15/drivers/mcb/
H A DKconfig33 tristate "LPC (non PCI) based MCB carrier"
37 This is a MCB carrier on a LPC or non PCI device.
/linux-6.15/Documentation/devicetree/bindings/arm/hisilicon/
H A Dlow-pin-count.yaml13 Hisilicon HiP06 SoCs implement a Low Pin Count (LPC) controller, which
17 LPC device node.
/linux-6.15/arch/sh/kernel/cpu/sh4a/
H A Dsetup-sh7757.c806 LPC, LPC5, LPC6, LPC7, LPC8, enumerator
871 INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0),
872 INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00),
873 INTC_VECT(LPC, 0xb20),
969 0, DMAC8_11, 0, PECI0, LPC, FRT, 0, TMR45,
1069 { INT2PRI5, 0, 32, 8, { TMR45, 0, FRT, LPC } },
/linux-6.15/drivers/mtd/spi-nor/controllers/
H A DKconfig14 Enable support for the NXP LPC SPI Flash Interface controller.
/linux-6.15/Documentation/devicetree/bindings/tpm/
H A Dtcg,tpm-tis-mmio.yaml15 one of them being LPC (via MMIO). The standard is named:
/linux-6.15/Documentation/devicetree/bindings/pinctrl/
H A Daspeed,ast2600-pinctrl.yaml105 - LPC
331 - LPC
/linux-6.15/Documentation/i2c/busses/
H A Di2c-sis630.rst52 LPC Controller (rev 36)
/linux-6.15/Documentation/devicetree/bindings/serial/
H A D8250.yaml204 configured. One possible data source is the LPC/eSPI mode bit. Only
212 The VUART LPC address. Only applicable to aspeed,ast2500-vuart.
/linux-6.15/drivers/vfio/pci/
H A DKconfig42 and LPC bridge config space.
/linux-6.15/Documentation/devicetree/bindings/clock/
H A Dlpc1850-ccu.txt36 specific LPC part. Check the user manual for your specific part.
H A Dlpc1850-cgu.txt42 specific LPC part. Base clocks are numbered from 0 to 27.
/linux-6.15/Documentation/core-api/
H A Ddma-isa-lpc.rst2 DMA with ISA and LPC devices
8 controller. Even though ISA is more or less dead today the LPC bus
/linux-6.15/drivers/platform/chrome/
H A DKconfig144 tristate "ChromeOS Embedded Controller (LPC)"
149 over an LPC bus, including the LPC Microchip EC (MEC) variant.
/linux-6.15/drivers/pinctrl/aspeed/
H A Dpinctrl-aspeed-g6.c1121 SIG_EXPR_LIST_DECL_SESG(AB7, LAD0, LPC, SIG_DESC_SET(SCU434, 16),
1127 SIG_EXPR_LIST_DECL_SESG(AB8, LAD1, LPC, SIG_DESC_SET(SCU434, 17),
1133 SIG_EXPR_LIST_DECL_SESG(AC8, LAD2, LPC, SIG_DESC_SET(SCU434, 18),
1139 SIG_EXPR_LIST_DECL_SESG(AC7, LAD3, LPC, SIG_DESC_SET(SCU434, 19),
1145 SIG_EXPR_LIST_DECL_SESG(AE7, LCLK, LPC, SIG_DESC_SET(SCU434, 20),
1151 SIG_EXPR_LIST_DECL_SESG(AF7, LFRAME, LPC, SIG_DESC_SET(SCU434, 21),
1165 SIG_EXPR_LIST_DECL_SESG(AD8, LPCRST, LPC, SIG_DESC_SET(SCU434, 23),
1170 FUNC_GROUP_DECL(LPC, AB7, AB8, AC8, AC7, AE7, AF7, AD8);
1970 ASPEED_PINCTRL_GROUP(LPC),
2212 ASPEED_PINCTRL_FUNC(LPC),

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