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Searched refs:KHZ (Results 1 – 14 of 14) sorted by relevance

/linux-6.15/drivers/phy/samsung/
H A Dphy-samsung-usb2.h19 #define KHZ 1000 macro
20 #define MHZ (KHZ * KHZ)
H A Dphy-exynos4x12-usb2.c137 case 9600 * KHZ: in exynos4x12_rate_to_clk()
146 case 19200 * KHZ: in exynos4x12_rate_to_clk()
H A Dphy-exynos5250-usb2.c146 case 9600 * KHZ: in exynos5250_rate_to_clk()
155 case 19200 * KHZ: in exynos5250_rate_to_clk()
H A Dphy-exynos5-usbdrd.c303 #define KHZ 1000 macro
304 #define MHZ (KHZ * KHZ)
440 case 9600 * KHZ: in exynos5_rate_to_clk()
449 case 19200 * KHZ: in exynos5_rate_to_clk()
/linux-6.15/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgk20a.h27 #define KHZ (1000) macro
28 #define MHZ (KHZ * 1000)
146 clk->parent_rate / KHZ); in gk20a_pllg_n_lo()
H A Dgk20a.c113 target_clk_f = rate * 2 / KHZ; in gk20a_pllg_calc_mnp()
114 ref_clk_f = clk->parent_rate / KHZ; in gk20a_pllg_calc_mnp()
195 target_clk_f / KHZ); in gk20a_pllg_calc_mnp()
205 target_freq / KHZ, pll->m, pll->n, pll->pl, in gk20a_pllg_calc_mnp()
530 clk->parent_rate / KHZ); in gk20a_clk_setup_slide()
635 clk->parent_rate / KHZ); in gk20a_clk_ctor()
H A Dgm20b.c490 u32 rate = gk20a_pllg_calc_rate(&clk->base, pll) / KHZ; in gm20b_dvfs_calc_safe_pll()
491 u32 parent_rate = clk->base.parent_rate / KHZ; in gm20b_dvfs_calc_safe_pll()
1046 (clk->base.parent_rate / KHZ)); in gm20b_clk_new()
/linux-6.15/drivers/cpufreq/
H A Dtegra194-cpufreq.c21 #define KHZ 1000 macro
23 #define CPUFREQ_TBL_STEP_HZ (50 * KHZ * KHZ)
95 opp = dev_pm_opp_find_freq_exact(dev, freq_khz * KHZ, true); in tegra_cpufreq_set_bw()
240 return nltbl->ref_clk_hz / KHZ * ndiv / (nltbl->pdiv * nltbl->mdiv); in map_ndiv_to_freq()
356 return (rate_mhz * KHZ); /* in KHz */ in tegra194_calculate_speed()
475 opp = dev_pm_opp_find_freq_exact(cpu_dev, pos->frequency * KHZ, false); in tegra_cpufreq_init_cpufreq_table()
481 ret = dev_pm_opp_enable(cpu_dev, pos->frequency * KHZ); in tegra_cpufreq_init_cpufreq_table()
/linux-6.15/drivers/devfreq/
H A Dtegra30-devfreq.c68 #define KHZ 1000 macro
70 #define KHZ_MAX (ULONG_MAX / KHZ)
254 u32 avg_band_freq = tegra->max_freq * ACTMON_DEFAULT_AVG_BAND / KHZ; in tegra_devfreq_update_avg_wmark()
412 tegra->cur_freq = data->new_rate / KHZ; in tegra_actmon_clk_notify_cb()
567 tegra->cur_freq = clk_get_rate(tegra->emc_clock) / KHZ; in tegra_actmon_resume()
668 stat->current_frequency = cur_freq * KHZ; in tegra_devfreq_get_dev_status()
724 *freq = target_freq * KHZ; in tegra_governor_get_target()
915 tegra->max_freq = rate / KHZ; in tegra_devfreq_probe()
/linux-6.15/arch/x86/kernel/
H A Dtsc.c42 #define KHZ 1000 macro
1097 art_base_clk.freq_khz /= KHZ; in detect_art()
1481 (unsigned long)cpu_khz / KHZ, in determine_cpu_tsc_frequencies()
1482 (unsigned long)cpu_khz % KHZ); in determine_cpu_tsc_frequencies()
1486 (unsigned long)tsc_khz / KHZ, in determine_cpu_tsc_frequencies()
1487 (unsigned long)tsc_khz % KHZ); in determine_cpu_tsc_frequencies()
1494 u64 lpj = (u64)tsc_khz * KHZ; in get_loops_per_jiffy()
/linux-6.15/drivers/i2c/busses/
H A Di2c-qcom-geni.c74 #define KHZ(freq) (1000 * freq) macro
151 {KHZ(100), 7, 10, 12, 26},
152 {KHZ(400), 2, 5, 11, 22},
153 {KHZ(1000), 1, 2, 8, 18},
159 {KHZ(100), 8, 14, 18, 40},
160 {KHZ(400), 4, 3, 11, 20},
161 {KHZ(1000), 2, 3, 6, 15},
815 gi2c->clk_freq_out = KHZ(100); in geni_i2c_probe()
/linux-6.15/drivers/clk/sophgo/
H A Dclk-sg2042-pll.c60 #define KHZ 1000UL macro
61 #define MHZ (KHZ * KHZ)
/linux-6.15/arch/arm/boot/dts/microchip/
H A Dat91-tse850-3.dts343 /* 4 */ "", "456KHZ", "VCTRL", "SYNCSEL",
/linux-6.15/Documentation/virt/kvm/x86/
H A Dtimekeeping.rst68 |------>| CLOCK OUT | ---------> 66.3 KHZ DRAM