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Searched refs:ITS (Results 1 – 25 of 33) sorted by relevance

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/linux-6.15/Documentation/virt/kvm/devices/
H A Darm-vgic-its.rst4 ARM Virtual Interrupt Translation Service (ITS)
51 See "ITS Reset State" section.
64 restore the ITS tables from guest RAM to ITS internal structures.
66 The GICV3 must be restored before the ITS and all ITS registers but
74 "ITS Restore Sequence".
85 -EACCES The virtual ITS is backed by a physical GICv4 ITS, and the
94 ITS register, relative to the ITS control frame base address
126 ITS Restore Sequence:
134 c) provide the ITS base address
147 ITS Table ABI REV0:
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H A Darm-vgic.rst18 device and guest ITS devices, see arm-vgic-v3.txt. It is not possible to
146 request the initialization of the VGIC or ITS, no additional parameter
/linux-6.15/Documentation/admin-guide/hw-vuln/
H A Dindirect-target-selection.rst3 Indirect Target Selection (ITS)
6 ITS is a vulnerability in some Intel CPUs that support Enhanced IBRS and were
7 released before Alder Lake. ITS may allow an attacker to control the prediction
10 ITS is assigned CVE-2024-28956 with a CVSS score of 4.7 (Medium).
28 Below is the list of ITS affected CPUs [#f2]_ [#f3]_:
53 - Intel Atom CPUs are not affected by ITS.
95 attacks. And it also mitigates RETs that are vulnerable to ITS.
121 off Disable ITS mitigation.
131 ITS.
133 force Force the ITS bug and deploy the default mitigation.
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/linux-6.15/arch/x86/kernel/cpu/
H A Dcommon.c1231 #define ITS BIT(8) macro
1246 VULNBL_INTEL_STEPS(INTEL_SKYLAKE_X, X86_STEP_MAX, MMIO | RETBLEED | GDS | ITS),
1250 VULNBL_INTEL_STEPS(INTEL_KABYLAKE_L, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS | ITS),
1252 VULNBL_INTEL_STEPS(INTEL_KABYLAKE, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS | ITS),
1255 VULNBL_INTEL_STEPS(INTEL_ICELAKE_D, X86_STEP_MAX, MMIO | GDS | ITS | ITS_NATIVE_ONLY),
1256 VULNBL_INTEL_STEPS(INTEL_ICELAKE_X, X86_STEP_MAX, MMIO | GDS | ITS | ITS_NATIVE_ONLY),
1257 VULNBL_INTEL_STEPS(INTEL_COMETLAKE, X86_STEP_MAX, MMIO | MMIO_SBDS | RETBLEED | GDS | ITS),
1258 VULNBL_INTEL_STEPS(INTEL_COMETLAKE_L, 0x0, MMIO | RETBLEED | ITS),
1260 VULNBL_INTEL_STEPS(INTEL_TIGERLAKE_L, X86_STEP_MAX, GDS | ITS | ITS_NATIVE_ONLY),
1261 VULNBL_INTEL_STEPS(INTEL_TIGERLAKE, X86_STEP_MAX, GDS | ITS | ITS_NATIVE_ONLY),
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/linux-6.15/Documentation/devicetree/bindings/misc/
H A Dfsl,qoriq-mc.yaml42 The msi-map property is used to associate the devices with both the ITS
48 For GICv3 and GIC ITS bindings, see:
104 Maps an ICID to a GIC ITS and associated msi-specifier
111 associated with the listed GIC ITS, with the msi-specifier
/linux-6.15/Documentation/devicetree/bindings/bus/
H A Dxlnx,versal-net-cdx.yaml20 are used to configure SMMU and GIC-ITS respectively.
27 device ID as well as the associated ITS controller.
/linux-6.15/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic-v3.yaml195 GICv3 has one or more Interrupt Translation Services (ITS) that are
203 Present if the GIC ITS permits programming shareability and
217 Specifies the base physical address and size of the ITS registers.
223 address and size of the pre-ITS window.
H A Dhisilicon,mbigen-v2.txt13 interrupt by writing ITS register.
/linux-6.15/arch/mips/alchemy/
H A DKconfig32 bool "Trapeze ITS GPR board"
H A DPlatform26 # Trapeze ITS GRP board
/linux-6.15/Documentation/arch/arm64/
H A Dsilicon-errata.rst217 | Cavium | ThunderX ITS | #22375,24313 | CAVIUM_ERRATUM_22375 |
219 | Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 |
270 | Qualcomm Tech. | QDF2400 ITS | E0065 | QCOM_QDF2400_ERRATUM_0065 |
/linux-6.15/Documentation/translations/zh_CN/arch/arm64/
H A Dsilicon-errata.txt73 | Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 |
/linux-6.15/Documentation/translations/zh_TW/arch/arm64/
H A Dsilicon-errata.txt77 | Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 |
/linux-6.15/arch/arm64/boot/dts/cavium/
H A Dthunder2-99xx.dtsi73 reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */
/linux-6.15/Documentation/tee/
H A Dts-tee.rst21 protocol. A TS SP can host one or more services (e.g. PSA Crypto, PSA ITS, etc).
/linux-6.15/arch/mips/boot/compressed/
H A DMakefile188 quiet_cmd_cpp_its_S = ITS $@
/linux-6.15/arch/mips/boot/
H A DMakefile129 quiet_cmd_cpp_its_S = ITS $@
/linux-6.15/arch/arm64/boot/dts/amd/
H A Delba.dtsi159 * Elba specific pre-ITS is enabled using the
/linux-6.15/Documentation/arch/arm/nwfpe/
H A Dnwfpe.rst73 AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
/linux-6.15/Documentation/devicetree/bindings/sound/
H A Dcirrus,cs42l42.yaml65 This is "inverted tip sense (ITS)" in the datasheet.
/linux-6.15/arch/m68k/fpsp040/
H A Dsatan.S291 |--WHILE THE DIVISION IS TAKING ITS TIME, WE FETCH ATAN(|F|)
/linux-6.15/arch/arm/nwfpe/
H A Dsoftfloat-specialize22 AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
/linux-6.15/Documentation/scsi/
H A DFlashPoint.rst13 MYLEX INTRODUCES LINUX OPERATING SYSTEM SUPPORT FOR ITS
/linux-6.15/Documentation/devicetree/bindings/iio/temperature/
H A Dadi,ltc2983.yaml248 3 - ITS-90
/linux-6.15/arch/arm64/
H A DKconfig1145 with a small impact affecting only ITS table allocation.
1150 The fixes are in ITS initialization and basically ignore memory access
1156 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
1160 ITS SYNC command hang for cross node io and collections/cpu mapping.
1241 when issued ITS commands such as VMOVP and VMAPP, and requires
1283 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
1329 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"

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