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Searched refs:INTEL_INFO (Results 1 – 24 of 24) sorted by relevance

/linux-6.15/drivers/gpu/drm/i915/
H A Di915_drv.h391 #define INTEL_INFO(i915) ((i915)->__info) macro
630 #define HAS_LLC(i915) (INTEL_INFO(i915)->has_llc)
639 (INTEL_INFO(i915)->has_logical_ring_contexts)
641 (INTEL_INFO(i915)->has_logical_ring_elsq)
661 (IS_SKYLAKE(i915) && (INTEL_INFO(i915)->gt == 3 || INTEL_INFO(i915)->gt == 4))
679 (INTEL_INFO(i915)->has_heci_pxp)
682 (INTEL_INFO(i915)->has_heci_gscfi)
690 (INTEL_INFO(i915)->has_oa_bpc_reporting)
692 (INTEL_INFO(i915)->has_oa_slice_contrib_limits)
694 (INTEL_INFO(i915)->has_oam)
[all …]
H A Dintel_device_info.c231 const struct intel_device_info *info = INTEL_INFO(i915); in intel_device_info_subplatform_init()
352 INTEL_INFO(i915)->platform == INTEL_METEORLAKE) { in intel_ipver_early_init()
418 memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime)); in intel_device_info_driver_create()
H A Di915_getparam.c191 value = INTEL_INFO(i915)->has_coherent_ggtt; in i915_getparam_ioctl()
H A Di915_driver.c388 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size; in i915_set_dma_info()
716 intel_platform_name(INTEL_INFO(dev_priv)->platform), in i915_welcome_messages()
718 INTEL_INFO(dev_priv)->platform), in i915_welcome_messages()
721 intel_device_info_print(INTEL_INFO(dev_priv), in i915_welcome_messages()
H A Dintel_clock_gating.c505 if (INTEL_INFO(i915)->gt == 1) in ivb_init_clock_gating()
H A Di915_debugfs.c71 intel_device_info_print(INTEL_INFO(i915), RUNTIME_INFO(i915), &p); in i915_capabilities()
H A Di915_gpu_error.c1999 INTEL_INFO(i915), in capture_gen()
2120 if (INTEL_INFO(i915)->has_gt_uc) { in __i915_gpu_coredump()
H A Di915_perf.c4963 enum intel_platform platform = INTEL_INFO(i915)->platform; in oa_init_supported_formats()
/linux-6.15/drivers/gpu/drm/i915/gt/
H A Dgen7_renderclear.c59 switch (INTEL_INFO(i915)->gt) { in batch_get_defaults()
74 switch (INTEL_INFO(i915)->gt) { in batch_get_defaults()
402 (((IS_IVYBRIDGE(i915) && INTEL_INFO(i915)->gt == 1) || in emit_batch()
H A Dintel_gt.c188 INTEL_INFO(i915)->gt == 3 ? in intel_gt_init_hw()
431 if (INTEL_INFO(gt->i915)->has_coherent_ggtt) in intel_gt_flush_ggtt_writes()
911 gt->info.engine_mask = INTEL_INFO(i915)->platform_engine_mask; in intel_gt_probe_all()
921 for (i = 1, gtdef = &INTEL_INFO(i915)->extra_gt_list[i - 1]; in intel_gt_probe_all()
923 i++, gtdef = &INTEL_INFO(i915)->extra_gt_list[i - 1]) { in intel_gt_probe_all()
H A Dintel_gt_mcr.c38 #define HAS_MSLICE_STEERING(i915) (INTEL_INFO(i915)->has_mslice_steering)
175 MISSING_CASE(INTEL_INFO(i915)->platform); in intel_gt_mcr_init()
H A Dintel_sseu.c577 switch (INTEL_INFO(i915)->gt) { in hsw_sseu_info_init()
579 MISSING_CASE(INTEL_INFO(i915)->gt); in hsw_sseu_info_init()
H A Dintel_reset.c811 return INTEL_INFO(gt->i915)->has_reset_engine; in intel_has_reset_engine()
1184 return INTEL_INFO(i915)->gpu_reset_clobbers_display; in intel_gt_gpu_reset_clobbers_display()
H A Dintel_workarounds.c421 (INTEL_INFO(i915)->gt == 3 ? HDC_FENCE_DEST_SLM_DISABLE : 0)); in bdw_ctx_workarounds_init()
2556 if (INTEL_INFO(i915)->gt == 1) in rcs_engine_wa_init()
2734 if (INTEL_INFO(i915)->tuning_thread_rr_after_dep) in add_render_compute_tuning_settings()
H A Dselftest_workarounds.c420 enum intel_platform platform = INTEL_INFO(engine->i915)->platform; in wo_register()
H A Dintel_rps.c381 if (INTEL_INFO(i915)->is_mobile) in pvid_to_extvid()
/linux-6.15/drivers/gpu/drm/xe/compat-i915-headers/
H A Di915_drv.h26 #define INTEL_INFO(dev_priv) (&((dev_priv)->info)) macro
/linux-6.15/drivers/gpu/drm/i915/selftests/
H A Dintel_uncore.c196 intel_platform_name(INTEL_INFO(gt->i915)->platform)); in live_forcewake_ops()
/linux-6.15/drivers/gpu/drm/i915/gt/uc/
H A Dintel_gsc_uc.c111 mask = INTEL_INFO(gt->i915)->platform_engine_mask; in gsc_engine_supported()
H A Dintel_huc.c271 mask = INTEL_INFO(gt->i915)->platform_engine_mask; in vcs_supported()
H A Dintel_uc_fw.c287 enum intel_platform p = INTEL_INFO(i915)->platform; in __uc_fw_auto_select()
/linux-6.15/drivers/gpu/drm/i915/gem/
H A Di915_gem_create.c415 max_pat_index = INTEL_INFO(i915)->max_pat_index; in ext_set_pat()
H A Di915_gem_object.c55 return INTEL_INFO(i915)->cachelevel_to_pat[level]; in i915_gem_get_pat_index()
H A Di915_gem_execbuffer.c1128 cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment; in reloc_cache_init()