Searched refs:INTEL_CX0_LANE1 (Results 1 – 1 of 1) sorted by relevance
32 #define INTEL_CX0_LANE1 BIT(1) macro33 #define INTEL_CX0_BOTH_LANES (INTEL_CX0_LANE1 | INTEL_CX0_LANE0)486 u8 lane_mask = lane == 0 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1; in intel_cx0_phy_set_signal_levels()2884 u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 : INTEL_CX0_LANE0; in intel_cx0_phy_lane_reset()2963 u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1; in intel_cx0_program_phy_lane()3011 u8 maxpclk_lane = lane_reversal ? INTEL_CX0_LANE1 : in __intel_cx0pll_enable()3301 u8 lane = dig_port->lane_reversal ? INTEL_CX0_LANE1 : INTEL_CX0_LANE0; in intel_cx0_pll_is_enabled()