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Searched refs:INSTPM (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/video/fbdev/i810/
H A Di810_regs.h51 #define INSTPM 0x020C0 macro
/linux-6.15/drivers/gpu/drm/xe/regs/
H A Dxe_engine_regs.h95 #define INSTPM(base) XE_REG((base) + 0xc0, XE_REG_OPTION_MASKED) macro
/linux-6.15/drivers/gpu/drm/i915/gvt/
H A Dmmio_context.c61 {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
93 {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
H A Dcmd_parser.c927 offset == i915_mmio_reg_offset(INSTPM))) in cmd_reg_handler()
/linux-6.15/drivers/gpu/drm/i915/
H A Dintel_clock_gating.c660 intel_uncore_write(&i915->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); in gen3_init_clock_gating()
H A Di915_reg.h488 #define INSTPM _MMIO(0x20c0) macro
/linux-6.15/drivers/gpu/drm/i915/gt/
H A Dintel_workarounds.c339 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); in gen6_ctx_workarounds_init()
345 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); in gen7_ctx_workarounds_init()
351 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); in gen8_ctx_workarounds_init()
/linux-6.15/drivers/gpu/drm/xe/
H A Dxe_wa.c762 XE_RTP_ACTIONS(SET(INSTPM(RENDER_RING_BASE), ENABLE_SEMAPHORE_POLL_BIT))
/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_display_debugfs.c98 sr_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN; in i915_sr_status()
H A Di9xx_wm.c183 was_enabled = intel_uncore_read(&dev_priv->uncore, INSTPM) & INSTPM_SELF_EN; in _intel_set_memory_cxsr()
186 intel_uncore_write(&dev_priv->uncore, INSTPM, val); in _intel_set_memory_cxsr()
187 intel_uncore_posting_read(&dev_priv->uncore, INSTPM); in _intel_set_memory_cxsr()