Searched refs:IMX95_CLK_SYSPLL1_PFD1_DIV2 (Results 1 – 3 of 3) sorted by relevance
808 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;822 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;1055 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;1069 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;1369 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;1659 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;1693 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;1733 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;1769 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;1780 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
19 #define IMX95_CLK_SYSPLL1_PFD1_DIV2 10 macro
1122 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;