Searched refs:IMX93_CLK_SYS_PLL_PFD1_DIV2 (Results 1 – 5 of 5) sorted by relevance
57 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,58 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,59 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
461 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;869 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;1133 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,1135 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;1159 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,1301 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;1323 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
611 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
15 #define IMX93_CLK_SYS_PLL_PFD1_DIV2 6 macro
301 clks[IMX93_CLK_SYS_PLL_PFD1_DIV2] = imx_clk_hw_fixed_factor("sys_pll_pfd1_div2", in imx93_clocks_probe()