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Searched refs:IMX8ULP_CLK_SPLL3_PFD1_DIV1 (Results 1 – 3 of 3) sorted by relevance

/linux-6.15/arch/arm64/boot/dts/freescale/
H A Dimx8ulp-evk.dts197 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>;
207 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>;
/linux-6.15/include/dt-bindings/clock/
H A Dimx8ulp-clock.h24 #define IMX8ULP_CLK_SPLL3_PFD1_DIV1 17 macro
/linux-6.15/drivers/clk/imx/
H A Dclk-imx8ulp.c189 …clks[IMX8ULP_CLK_SPLL3_PFD1_DIV1] = imx_clk_hw_divider("spll3_pfd1_div1", "spll3_pfd1_div1_gate", … in imx8ulp_clk_cgc1_init()