Home
last modified time | relevance | path

Searched refs:ICE_M (Results 1 – 5 of 5) sorted by relevance

/linux-6.15/drivers/net/ethernet/intel/ice/
H A Dice_hw_autogen.h20 #define QTX_COMM_HEAD_HEAD_M ICE_M(0x1FFF, 0)
24 #define PF_FW_ARQH_ARQH_M ICE_M(0x3FF, 0)
26 #define PF_FW_ARQLEN_ARQLEN_M ICE_M(0x3FF, 0)
35 #define PF_FW_ATQH_ATQH_M ICE_M(0x3FF, 0)
37 #define PF_FW_ATQLEN_ATQLEN_M ICE_M(0x3FF, 0)
48 #define PF_MBX_ARQH_ARQH_M ICE_M(0x3FF, 0)
57 #define PF_MBX_ATQH_ATQH_M ICE_M(0x3FF, 0)
73 #define PF_SB_ARQH_ARQH_M ICE_M(0x3FF, 0)
87 #define PF_SB_ARQT_ARQT_M ICE_M(0x3FF, 0)
96 #define PF_SB_ATQH_ATQH_M ICE_M(0x3FF, 0)
[all …]
H A Dice_ptp_hw.h479 #define TS_CMD_RX_TYPE ICE_M(0x18, 0x4)
504 #define Q_REG_FIFO02_M ICE_M(0x3FF, 0)
506 #define Q_REG_FIFO13_M ICE_M(0x3FF, 10)
615 #define P_REG_LINK_SPEED_SERDES_M ICE_M(0x7, 0)
778 #define PHY_MAC_XIF_1STEP_ENA_M ICE_M(0x1, 5)
779 #define PHY_MAC_XIF_TS_BIN_MODE_M ICE_M(0x1, 11)
780 #define PHY_MAC_XIF_TS_SFD_ENA_M ICE_M(0x1, 20)
781 #define PHY_MAC_XIF_GMII_TS_SEL_M ICE_M(0x1, 21)
801 #define PHY_MAC_TSU_CFG_RX_MODE_M ICE_M(0x7, 0)
804 #define PHY_MAC_TSU_CFG_TX_MODE_M ICE_M(0x7, 12)
[all …]
H A Dice_adminq_cmd.h183 #define ICE_AQC_MAN_MAC_WR_M ICE_M(3, ICE_AQC_MAN_MAC_WR_S)
1162 #define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0)
1187 #define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0)
1231 #define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0)
1340 #define ICE_AQ_FEC_MASK ICE_M(0x7, 0)
1748 #define ICE_AQC_NVM_ACTIV_SEL_MASK ICE_M(0x7, 3)
2368 ICE_M(0x7, ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT)
2397 ICE_M(0x7, ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT)
2400 ICE_M(0x3, ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT)
2427 ICE_M(0x7, ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT)
[all …]
H A Dice_osdep.h31 #define ICE_M(m, s) ((m ## U) << (s)) macro
H A Dice_type.h321 #define ICE_TS_CLK_FREQ_M ICE_M(0x7, ICE_TS_CLK_FREQ_S)
365 #define ICE_TS_TMR1_OWNR_M ICE_M(0x7, ICE_TS_TMR1_OWNR_S)
1170 #define ICE_LINK_TOPO_NODE_COUNT_M ICE_M(0x3FF, 0)