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Searched refs:I915_MAX_PIPES (Results 1 – 25 of 25) sorted by relevance

/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_bw.h28 struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES];
58 int min_cdclk[I915_MAX_PIPES];
59 unsigned int data_rate[I915_MAX_PIPES];
60 u8 num_active_planes[I915_MAX_PIPES];
H A Dintel_display_irq.h73 void i9xx_pipestat_irq_ack(struct drm_i915_private *i915, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
75 … i915_pipestat_irq_handler(struct drm_i915_private *i915, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
76 … i965_pipestat_irq_handler(struct drm_i915_private *i915, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
77 void valleyview_pipestat_irq_handler(struct drm_i915_private *i915, u32 pipe_stats[I915_MAX_PIPES]);
H A Dskl_watermark.h69 struct skl_ddb_entry ddb[I915_MAX_PIPES];
70 unsigned int weight[I915_MAX_PIPES];
71 u8 slices[I915_MAX_PIPES];
H A Dintel_display_trace.h49 static_assert(I915_MAX_PIPES - 1 == _TRACE_PIPE_D);
75 __array(u32, frame, I915_MAX_PIPES)
76 __array(u32, scanline, I915_MAX_PIPES)
84 sizeof(__entry->frame[0]) * I915_MAX_PIPES);
86 sizeof(__entry->scanline[0]) * I915_MAX_PIPES);
104 __array(u32, frame, I915_MAX_PIPES)
105 __array(u32, scanline, I915_MAX_PIPES)
114 sizeof(__entry->frame[0]) * I915_MAX_PIPES);
234 __array(u32, frame, I915_MAX_PIPES)
235 __array(u32, scanline, I915_MAX_PIPES)
[all …]
H A Dintel_cdclk.h45 int min_cdclk[I915_MAX_PIPES];
47 u8 min_voltage_level[I915_MAX_PIPES];
H A Dintel_display.h208 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
391 … (i) < (I915_MAX_PIPES * 2) && ((crtc) = intel_crtc_for_pipe(display, (i) % I915_MAX_PIPES), 1); \
393 for_each_if((crtc) && ((first_pipes) | ((second_pipes) << I915_MAX_PIPES)) & BIT(i))
396 for ((i) = (I915_MAX_PIPES * 2 - 1); \
397 (i) >= 0 && ((crtc) = intel_crtc_for_pipe(display, (i) % I915_MAX_PIPES), 1); \
399 for_each_if((crtc) && ((first_pipes) | ((second_pipes) << I915_MAX_PIPES)) & BIT(i))
H A Dintel_display_core.h472 u32 de_irq_mask[I915_MAX_PIPES];
473 u32 pipestat_irq_mask[I915_MAX_PIPES];
549 u32 chv_dpll_md[I915_MAX_PIPES];
H A Dintel_link_bw.h20 int max_bpp_x16[I915_MAX_PIPES];
H A Dintel_display_device.h265 u8 num_sprites[I915_MAX_PIPES];
266 u8 num_scalers[I915_MAX_PIPES];
298 u32 cursor_offsets[I915_MAX_PIPES];
H A Dintel_display_limits.h23 I915_MAX_PIPES = _PIPE_EDP enumerator
H A Dintel_frontbuffer.c338 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > in intel_frontbuffer_track()
340 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); in intel_frontbuffer_track()
H A Dintel_dp_tunnel.c20 struct drm_dp_tunnel_ref ref[I915_MAX_PIPES];
472 drm_WARN_ON(display->drm, pipe_mask & ~((1 << I915_MAX_PIPES) - 1)); in intel_dp_tunnel_atomic_add_group_state()
H A Dintel_plane_initial.c424 struct intel_initial_plane_config plane_configs[I915_MAX_PIPES] = {}; in intel_initial_plane_config()
H A Dintel_display_irq.c528 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) in i9xx_pipestat_irq_ack() argument
596 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) in i915_pipestat_irq_handler() argument
621 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) in i965_pipestat_irq_handler() argument
649 u32 pipe_stats[I915_MAX_PIPES]) in valleyview_pipestat_irq_handler() argument
H A Dintel_dvo.c423 u32 dpll[I915_MAX_PIPES]; in intel_dvo_init_dev()
H A Dintel_pmdemand.c38 int ddi_clocks[I915_MAX_PIPES];
H A Dintel_display_types.h1740 struct intel_dp_mst_encoder *stream_encoders[I915_MAX_PIPES];
H A Dskl_watermark.c864 u8 dbuf_mask[I915_MAX_PIPES];
3782 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; in skl_dbuf_is_misconfigured()
3803 I915_MAX_PIPES, crtc->pipe)) in skl_dbuf_is_misconfigured()
H A Dintel_display_device.c1718 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->pipe_mask) < I915_MAX_PIPES); in __intel_display_device_info_runtime_init()
H A Dintel_display.c6886 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; in skl_commit_modeset_enables()
6938 entries, I915_MAX_PIPES, pipe)) in skl_commit_modeset_enables()
7027 entries, I915_MAX_PIPES, pipe)); in skl_commit_modeset_enables()
7237 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {}; in intel_atomic_commit_tail()
/linux-6.15/drivers/gpu/drm/i915/gvt/
H A Dfb_decoder.c194 for (i = 0; i < I915_MAX_PIPES; i++) in get_active_pipe()
219 if (pipe >= I915_MAX_PIPES) in intel_vgpu_decode_primary_plane()
351 if (pipe >= I915_MAX_PIPES) in intel_vgpu_decode_cursor_plane()
H A Dgvt.h116 DECLARE_BITMAP(flip_done_event[I915_MAX_PIPES],
H A Ddisplay.c88 pipe < PIPE_A || pipe >= I915_MAX_PIPES)) in pipe_is_enabled()
/linux-6.15/drivers/gpu/drm/i915/
H A Di915_irq.c245 u32 pipe_stats[I915_MAX_PIPES] = {}; in valleyview_irq_handler()
339 u32 pipe_stats[I915_MAX_PIPES] = {}; in cherryview_irq_handler()
964 u32 pipe_stats[I915_MAX_PIPES] = {}; in i915_irq_handler()
1087 u32 pipe_stats[I915_MAX_PIPES] = {}; in i965_irq_handler()
/linux-6.15/drivers/gpu/drm/xe/display/
H A Dxe_plane_initial.c287 struct intel_initial_plane_config plane_configs[I915_MAX_PIPES] = {}; in intel_initial_plane_config()