Searched refs:HOST2XTENSA_INTR_ENABLE (Results 1 – 1 of 1) sorted by relevance
39 #define HOST2XTENSA_INTR_ENABLE BIT(0) macro135 writel(HOST2XTENSA_INTR_ENABLE, core->reg_base + CPU_CS_H2XSOFTINTEN); in iris_vpu_boot_firmware()