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Searched refs:HHI_VID_PLL_CLK_DIV (Results 1 – 6 of 6) sorted by relevance

/linux-6.15/drivers/gpu/drm/meson/
H A Dmeson_vclk.c50 #define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */ macro
207 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
211 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
214 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
216 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
218 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
222 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
224 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
226 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
229 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
[all …]
/linux-6.15/drivers/clk/meson/
H A Daxg.h69 #define HHI_VID_PLL_CLK_DIV 0x1a0 macro
H A Dgxbb.h52 #define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */ macro
H A Dg12a.h69 #define HHI_VID_PLL_CLK_DIV 0x1A0 macro
H A Dgxbb.c1774 .reg_off = HHI_VID_PLL_CLK_DIV,
1779 .reg_off = HHI_VID_PLL_CLK_DIV,
1817 .offset = HHI_VID_PLL_CLK_DIV,
1836 .offset = HHI_VID_PLL_CLK_DIV,
H A Dg12a.c2649 .reg_off = HHI_VID_PLL_CLK_DIV,
2654 .reg_off = HHI_VID_PLL_CLK_DIV,
2675 .offset = HHI_VID_PLL_CLK_DIV,
2694 .offset = HHI_VID_PLL_CLK_DIV,