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Searched refs:HHI_HDMI_PLL_CNTL2 (Results 1 – 4 of 4) sorted by relevance

/linux-6.15/drivers/gpu/drm/meson/
H A Dmeson_vclk.c101 #define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ macro
250 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00404e00); in meson_venci_cvbs_clock_config()
263 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb300); in meson_venci_cvbs_clock_config()
280 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00010000); in meson_venci_cvbs_clock_config()
502 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
505 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
522 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb000 | frac); in meson_hdmi_pll_set_params()
545 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, frac); in meson_hdmi_pll_set_params()
590 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
601 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
[all …]
/linux-6.15/drivers/clk/meson/
H A Dgxbb.h98 #define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ macro
H A Dg12a.h116 #define HHI_HDMI_PLL_CNTL2 0x328 macro
H A Dgxbb.c181 .reg_off = HHI_HDMI_PLL_CNTL2,
235 .reg_off = HHI_HDMI_PLL_CNTL2,
267 .offset = HHI_HDMI_PLL_CNTL2,
285 .offset = HHI_HDMI_PLL_CNTL2,
303 .offset = HHI_HDMI_PLL_CNTL2,