Searched refs:GTR (Results 1 – 5 of 5) sorted by relevance
13 This binding describes the Xilinx ZynqMP Gigabit Transceiver (GTR) PHY. The14 GTR provides four lanes and is used by USB, SATA, PCIE, Display port and23 - description: The GTR lane
6 model = "SolidRun Clearfog GTR S4";
6 model = "SolidRun Clearfog GTR L8";
3 * Device Tree file for Clearfog GTR machines rev 1.0 (88F6825)
97 #define GTR (1<<2) /* globally enable IO traps */ macro