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/linux-6.15/Documentation/devicetree/bindings/interrupt-controller/
H A Dmti,gic.yaml14 The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
16 interrupts which can be used as IPIs. The GIC also includes a free-running
28 GIC interrupt number. The 3d cell encodes the interrupt flags setting up
34 Base address and length of the GIC registers space. If not present,
42 Specifies the list of CPU interrupt vectors to which the GIC may not
55 Specifies the range of GIC interrupts that are reserved for IPIs.
69 MIPS GIC includes a free-running global timer, per-CPU count/compare
70 timers, and a watchdog. Currently only the GIC Timer is supported.
77 Interrupt for the GIC local timer, so normally it's suppose to be of
H A Darm,gic.yaml13 ARM SMP cores are often associated with a GIC, providing per processor
17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
88 the 8 possible cpus attached to the GIC. A bit set to '1' indicated
97 Specifies base physical address(s) and size of the GIC registers. The
99 is the GIC cpu interface register base and size.
103 registers. The first additional region is the GIC virtual interface
104 control register base and size. The 2nd additional region is the GIC
113 secondary GICs, or VGIC maintenance interrupt on primary GIC (see "GICv2
119 regions, used when the GIC doesn't have banked registers. The offset
128 description: List of names for the GIC clock input(s). Valid clock names
[all …]
H A Dmarvell,gicp.txt4 GICP is a Marvell extension of the GIC that allows to trigger GIC SPI
7 into GIC SPI interrupts.
15 - marvell,spi-ranges: tuples of GIC SPI interrupts ranges available
H A Dbrcm,bcm7120-l2-intc.yaml14 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
34 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
36 0 -----[ MUX ] ------------|==========> GIC interrupt 75
39 1 -----[ MUX ] --------)---|==========> GIC interrupt 76
42 2 -----[ MUX ] --------)---|==========> GIC interrupt 77
48 7 ---------------------|---|===========> GIC interrupt 66
54 |===========> GIC interrupt 64
H A Dti,omap4-wugen-mpu.txt4 routes interrupts to the GIC, and also serves as a wakeup source. It
18 - Because this HW ultimately routes interrupts to the GIC, the
19 interrupt specifier must be that of the GIC.
H A Darm,gic-v3.yaml73 Specifies base physical address(s) and size of the GIC
75 - GIC Distributor interface (GICD)
76 - GIC Redistributors (GICR), one range per redistributor region
77 - GIC CPU interface (GICC)
78 - GIC Hypervisor interface (GICH)
79 - GIC Virtual CPU interface (GICV)
111 Present if the GIC redistributors permit programming shareability
178 GICR registers when the GIC redistributors are powered off.
203 Present if the GIC ITS permits programming shareability and
H A Dsocionext,uniphier-aidet.yaml10 UniPhier AIDET (ARM Interrupt Detector) is an add-on block for ARM GIC
11 (Generic Interrupt Controller). GIC itself can handle only high level and
43 interrupt number of GIC). The second cell specifies the trigger type as
H A Dnvidia,tegra20-ictlr.txt4 interrupts to the GIC, and also serves as a wakeup source. It is also
25 - Because this HW ultimately routes interrupts to the GIC, the
26 interrupt specifier must be that of the GIC.
H A Drenesas,rza1-irqc.yaml14 The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas RZ/A1 and
16 - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI interrupts,
43 description: Specifies the mapping from external interrupts to GIC interrupts.
H A Dqcom,mpm.yaml17 one of these interrupts occur and replays it to GIC interrupt controller
18 after GIC becomes operational.
64 A set of MPM pin numbers and the corresponding GIC SPIs.
69 - description: GIC SPI number for the MPM pin
H A Dqcom,pdc.yaml17 well detect interrupts when the GIC is non-operational.
19 GIC is parent interrupt controller at the highest level. Platform interrupt
23 with the GIC interrupt. See example below.
74 - description: GIC hwirq number for the PDC port
H A Dmarvell,icu.txt6 communicating them to the GIC in the AP, the unit translates interrupt
7 requests on input wires to MSG memory mapped transactions to the GIC.
8 These messages will access a different GIC memory area depending on
39 - msi-parent: Should point to the GICP controller, the GIC extension
H A Dmarvell,armada-8k-pic.txt6 typically connected to the GIC as the primary interrupt controller.
15 typically the GIC
H A Dmarvell,odmi-controller.txt23 - marvell,spi-base : List of GIC base SPI interrupts, one for each
27 for details about the GIC Device Tree binding.
H A Dmstar,mst-intc.yaml14 interrupt controllers that routes interrupts to the GIC.
28 Use the same format as specified by GIC in arm,gic.yaml.
H A Dmediatek,mtk-cirq.yaml14 work outside of MCUSYS which comprises with Cortex-Ax cores, CCI and GIC.
16 to GIC in MCUSYS. When CIRQ is enabled, it will record the edge-sensitive
H A Daspeed,ast2700-intc.yaml39 INTC0 is used to assert GIC if interrupt in INTC1 asserted.
42 | GIC |---| INTC0 |--+--| INTC1_0 |---module2
H A Dfsl,ls-extirq.yaml49 description: Specifies the mapping from external interrupts to GIC interrupts.
105 # in parent interrupt controller, such as GIC.
/linux-6.15/Documentation/ABI/testing/
H A Dsysfs-bus-platform-devices-ampere-smpro65 …| GIC (other) | 5 | 0 | ERR0 | 0 …
67 …| GIC (other) | 5 | 1 | ERR1 | 0 …
69 …| GIC (other) | 5 | 2 | ERR2 | 0 …
71 …| GIC (other) | 5 | 3 | ERR3 | 0 …
73 …| GIC (other) | 5 | 4 | ERR4 | 0 …
75 …| GIC (other) | 5 | 5 | ERR5 | 0 …
77 …| GIC (other) | 5 | 6 | ERR6 | 0 …
79 …| GIC (other) | 5 | 7 | ERR7 | 0 …
81 …| GIC (other) | 5 | 8 | ERR8 | 0 …
83 …| GIC (other) | 5 | 9 | ERR9 | 0 …
[all …]
/linux-6.15/drivers/net/ethernet/renesas/
H A Dravb_ptp.c194 ravb_modify(ndev, GIC, GIC_PTCE, on ? GIC_PTCE : 0); in ravb_ptp_extts()
250 ravb_modify(ndev, GIC, GIC_PTME, GIC_PTME); in ravb_ptp_perout()
262 ravb_modify(ndev, GIC, GIC_PTME, 0); in ravb_ptp_perout()
303 gis &= ravb_read(ndev, GIC); in ravb_ptp_interrupt()
346 ravb_write(ndev, 0, GIC); in ravb_ptp_stop()
/linux-6.15/arch/mips/boot/dts/mti/
H A Dsead3.dts64 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
227 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; /* GIC 3 or CPU 4 */
242 interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; /* GIC 2 or CPU 4 */
253 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
/linux-6.15/Documentation/virt/kvm/devices/
H A Darm-vgic.rst27 Base address in the guest physical address space of the GIC distributor
32 Base address in the guest physical address space of the GIC virtual cpu
110 a GIC without the security extensions expose group 0 and group 1 active
132 this GIC instance, ranging from 64 to 1024, in increments of 32.
138 -EBUSY Value has already be set, or GIC has already been initialized
H A Dvcpu.rst51 -ENODEV PMUv3 not supported or GIC not initialized
58 virtual GIC implementation, this must be done after initializing the in-kernel
70 -ENODEV PMUv3 not supported or GIC not initialized
120 -ENODEV PMUv3 not supported or GIC not initialized
159 in-kernel virtual GIC. These must be a PPI (16 <= intid < 32). Setting the
/linux-6.15/Documentation/devicetree/bindings/arm/freescale/
H A Dfsl,vf610-mscm-ir.txt19 Flags get passed only when using GIC as parent. Flags
20 encoding as documented by the GIC bindings.
/linux-6.15/arch/arm/boot/dts/arm/
H A Darm-realview-eb.dts34 * This is the core tile with the CPU and GIC etc for the
64 * to the GIC on the core tile.

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