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Searched refs:GENMASK_ULL (Results 1 – 25 of 383) sorted by relevance

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/linux-6.15/drivers/infiniband/hw/irdma/
H A Ddefs.h486 #define IRDMACQ_QPID GENMASK_ULL(55, 32)
493 #define IRDMACQ_OP GENMASK_ULL(61, 56)
732 #define IRDMAQPC_TTL GENMASK_ULL(7, 0)
737 #define IRDMAQPC_TOS GENMASK_ULL(31, 24)
758 #define IRDMAQPC_PKEY GENMASK_ULL(47, 32)
760 #define IRDMAQPC_QKEY GENMASK_ULL(63, 32)
767 #define IRDMAQPC_ISN GENMASK_ULL(55, 32)
769 #define IRDMAQPC_LSN GENMASK_ULL(55, 32)
772 #define IRDMAQPC_EPSN GENMASK_ULL(23, 0)
778 #define IRDMAQPC_SRTT GENMASK_ULL(31, 0)
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H A Duda_d.h25 #define IRDMA_UDA_QPSQ_AHIDX GENMASK_ULL(16, 0)
26 #define IRDMA_UDA_QPSQ_PROTOCOL GENMASK_ULL(23, 16)
29 #define IRDMA_UDA_QPSQ_MACLEN GENMASK_ULL(62, 56)
31 #define IRDMA_UDA_QPSQ_IPLEN GENMASK_ULL(54, 48)
33 #define IRDMA_UDA_QPSQ_L4T GENMASK_ULL(31, 30)
35 #define IRDMA_UDA_QPSQ_IIPT GENMASK_ULL(29, 28)
41 #define IRDMA_UDA_QPSQ_IMMDATA GENMASK_ULL(63, 0)
78 #define IRDMA_UDAQPC_IPID GENMASK_ULL(47, 32)
79 #define IRDMA_UDAQPC_SNDMSS GENMASK_ULL(29, 16)
80 #define IRDMA_UDAQPC_VLANTAG GENMASK_ULL(15, 0)
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/linux-6.15/drivers/iommu/riscv/
H A Diommu-bits.h26 #define RISCV_IOMMU_PPN_FIELD GENMASK_ULL(53, 10)
27 #define RISCV_IOMMU_QUEUE_LOG2SZ_FIELD GENMASK_ULL(4, 0)
28 #define RISCV_IOMMU_QUEUE_INDEX_FIELD GENMASK_ULL(31, 0)
36 #define RISCV_IOMMU_ATP_PPN_FIELD GENMASK_ULL(43, 0)
37 #define RISCV_IOMMU_ATP_MODE_FIELD GENMASK_ULL(63, 60)
276 #define RISCV_IOMMU_ICVEC_CIV GENMASK_ULL(3, 0)
277 #define RISCV_IOMMU_ICVEC_FIV GENMASK_ULL(7, 4)
278 #define RISCV_IOMMU_ICVEC_PMIV GENMASK_ULL(11, 8)
462 #define RISCV_IOMMU_CMD_OPCODE GENMASK_ULL(6, 0)
463 #define RISCV_IOMMU_CMD_FUNC GENMASK_ULL(9, 7)
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/linux-6.15/drivers/net/ethernet/marvell/octeontx2/af/
H A Dcgx_fw_if.h170 #define EVTREG_ID GENMASK_ULL(8, 3)
177 #define EVTREG_ERRTYPE GENMASK_ULL(18, 9)
182 #define RESP_MAJOR_VER GENMASK_ULL(12, 9)
183 #define RESP_MINOR_VER GENMASK_ULL(16, 13)
188 #define RESP_MAC_ADDR GENMASK_ULL(56, 9)
203 #define RESP_FWD_BASE GENMASK_ULL(56, 9)
228 #define RESP_LINKSTAT_UP GENMASK_ULL(9, 9)
240 #define CMDREG_ID GENMASK_ULL(7, 2)
249 #define CMDMTU_SIZE GENMASK_ULL(23, 8)
256 #define CMDSETFEC GENMASK_ULL(9, 8)
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H A Dnpc.h417 #define NPC_EXACT_NIBBLE GENMASK_ULL(43, 40)
426 #define NPC_EXACT_RESULT_OPC GENMASK_ULL(2, 1)
431 #define NPC_PARSE_NIBBLE GENMASK_ULL(30, 0)
474 #define RX_VTAG0_LID_MASK GENMASK_ULL(10, 8)
478 #define RX_VTAG1_LID_MASK GENMASK_ULL(42, 40)
482 #define TX_VTAG0_DEF_MASK GENMASK_ULL(25, 16)
483 #define TX_VTAG0_OP_MASK GENMASK_ULL(13, 12)
484 #define TX_VTAG0_LID_MASK GENMASK_ULL(10, 8)
486 #define TX_VTAG1_DEF_MASK GENMASK_ULL(57, 48)
487 #define TX_VTAG1_OP_MASK GENMASK_ULL(45, 44)
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H A Drvu_npc_hash.h104 GENMASK_ULL(63, 0),
105 GENMASK_ULL(63, 0),
108 GENMASK_ULL(63, 0),
109 GENMASK_ULL(63, 0),
115 GENMASK_ULL(63, 0),
116 GENMASK_ULL(63, 0),
119 GENMASK_ULL(63, 0),
120 GENMASK_ULL(63, 0),
127 [0] = GENMASK_ULL(63, 32), /* MSB 32 bit is mask and LSB 32 bit is offset. */
128 [1] = GENMASK_ULL(63, 32), /* MSB 32 bit is mask and LSB 32 bit is offset. */
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/linux-6.15/drivers/iommu/arm/arm-smmu-v3/
H A Darm-smmu-v3.h243 #define STRTAB_STE_0_CFG GENMASK_ULL(3, 1)
399 #define CMDQ_0_OP GENMASK_ULL(7, 0)
454 #define EVTQ_0_ID GENMASK_ULL(7, 0)
470 #define EVTQ_0_SSID GENMASK_ULL(31, 12)
471 #define EVTQ_0_SID GENMASK_ULL(63, 32)
472 #define EVTQ_1_STAG GENMASK_ULL(15, 0)
478 #define EVTQ_1_CLASS GENMASK_ULL(41, 40)
481 #define EVTQ_2_ADDR GENMASK_ULL(63, 0)
482 #define EVTQ_3_IPA GENMASK_ULL(51, 12)
490 #define PRIQ_0_SID GENMASK_ULL(31, 0)
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/linux-6.15/drivers/platform/mellanox/
H A Dmlxbf-tmfifo-regs.h18 #define MLXBF_TMFIFO_TX_STS__COUNT_RMASK GENMASK_ULL(8, 0)
19 #define MLXBF_TMFIFO_TX_STS__COUNT_MASK GENMASK_ULL(8, 0)
25 #define MLXBF_TMFIFO_TX_CTL__LWM_RMASK GENMASK_ULL(7, 0)
26 #define MLXBF_TMFIFO_TX_CTL__LWM_MASK GENMASK_ULL(7, 0)
30 #define MLXBF_TMFIFO_TX_CTL__HWM_RMASK GENMASK_ULL(7, 0)
31 #define MLXBF_TMFIFO_TX_CTL__HWM_MASK GENMASK_ULL(15, 8)
43 #define MLXBF_TMFIFO_RX_STS__COUNT_RMASK GENMASK_ULL(8, 0)
50 #define MLXBF_TMFIFO_RX_CTL__LWM_RMASK GENMASK_ULL(7, 0)
51 #define MLXBF_TMFIFO_RX_CTL__LWM_MASK GENMASK_ULL(7, 0)
55 #define MLXBF_TMFIFO_RX_CTL__HWM_RMASK GENMASK_ULL(7, 0)
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/linux-6.15/drivers/mmc/host/
H A Dcavium.h133 #define MIO_EMM_CMD_BUS_ID GENMASK_ULL(61, 60)
136 #define MIO_EMM_CMD_OFFSET GENMASK_ULL(54, 49)
137 #define MIO_EMM_CMD_CTYPE_XOR GENMASK_ULL(42, 41)
139 #define MIO_EMM_CMD_IDX GENMASK_ULL(37, 32)
140 #define MIO_EMM_CMD_ARG GENMASK_ULL(31, 0)
143 #define MIO_EMM_DMA_BUS_ID GENMASK_ULL(61, 60)
147 #define MIO_EMM_DMA_THRES GENMASK_ULL(56, 51)
152 #define MIO_EMM_DMA_CARD_ADDR GENMASK_ULL(31, 0)
161 #define MIO_EMM_DMA_CFG_SIZE GENMASK_ULL(55, 36)
162 #define MIO_EMM_DMA_CFG_ADR GENMASK_ULL(35, 0)
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/linux-6.15/drivers/fpga/
H A Ddfl.h72 #define DFH_ID GENMASK_ULL(11, 0) /* Feature ID */
75 #define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */
78 #define DFH_VERSION GENMASK_ULL(59, 52) /* DFH version */
79 #define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */
116 #define DFHv1_PARAM_MSI_X_NUMV GENMASK_ULL(63, 32)
117 #define DFHv1_PARAM_MSI_X_STARTV GENMASK_ULL(31, 0)
140 #define FME_CAP_NUM_PORTS GENMASK_ULL(19, 17) /* Number of ports */
143 #define FME_CAP_CACHE_ASSOC GENMASK_ULL(47, 44) /* Associativity */
147 #define FME_PORT_OFST_DFH_OFST GENMASK_ULL(23, 0)
149 #define FME_PORT_OFST_BAR_ID GENMASK_ULL(34, 32)
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/linux-6.15/tools/perf/util/arm-spe-decoder/
H A Darm-spe-pkt-decoder.h45 #define SPE_HEADER0_MASK1 (GENMASK_ULL(7, 6) | GENMASK_ULL(3, 0))
49 #define SPE_HEADER0_MASK2 GENMASK_ULL(7, 2)
55 #define SPE_HEADER0_MASK3 GENMASK_ULL(7, 3)
60 #define SPE_HDR_SHORT_INDEX(h) ((h) & GENMASK_ULL(2, 0))
73 #define SPE_ADDR_PKT_ADDR_GET_BYTES_0_6(v) ((v) & GENMASK_ULL(55, 0))
77 #define SPE_ADDR_PKT_GET_EL(v) (((v) & GENMASK_ULL(62, 61)) >> 61)
79 #define SPE_ADDR_PKT_GET_PAT(v) (((v) & GENMASK_ULL(59, 56)) >> 56)
87 #define SPE_CTX_PKT_HDR_INDEX(h) ((h) & GENMASK_ULL(1, 0))
114 #define SPE_OP_PKT_HDR_CLASS(h) ((h) & GENMASK_ULL(1, 0))
121 #define SPE_OP_PKT_LDST_SUBCLASS_GET(v) ((v) & GENMASK_ULL(7, 1))
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/linux-6.15/drivers/net/wireless/realtek/rtw89/
H A Dwow.h8 #define RTW89_KEY_PN_0 GENMASK_ULL(7, 0)
9 #define RTW89_KEY_PN_1 GENMASK_ULL(15, 8)
10 #define RTW89_KEY_PN_2 GENMASK_ULL(23, 16)
11 #define RTW89_KEY_PN_3 GENMASK_ULL(31, 24)
12 #define RTW89_KEY_PN_4 GENMASK_ULL(39, 32)
13 #define RTW89_KEY_PN_5 GENMASK_ULL(47, 40)
15 #define RTW89_IGTK_IPN_0 GENMASK_ULL(7, 0)
16 #define RTW89_IGTK_IPN_1 GENMASK_ULL(15, 8)
17 #define RTW89_IGTK_IPN_2 GENMASK_ULL(23, 16)
18 #define RTW89_IGTK_IPN_3 GENMASK_ULL(31, 24)
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/linux-6.15/drivers/infiniband/hw/erdma/
H A Derdma_hw.h102 #define ERDMA_CQDB_IDX_MASK GENMASK_ULL(63, 56)
103 #define ERDMA_CQDB_CQN_MASK GENMASK_ULL(55, 32)
106 #define ERDMA_CQDB_CMDSN_MASK GENMASK_ULL(29, 28)
107 #define ERDMA_CQDB_CI_MASK GENMASK_ULL(23, 0)
110 #define ERDMA_EQDB_CI_MASK GENMASK_ULL(23, 0)
174 #define ERDMA_CMD_HDR_SUB_MOD_MASK GENMASK_ULL(25, 24)
175 #define ERDMA_CMD_HDR_OPCODE_MASK GENMASK_ULL(23, 16)
580 #define ERDMA_SQE_HDR_QPN_MASK GENMASK_ULL(51, 32)
581 #define ERDMA_SQE_HDR_OPCODE_MASK GENMASK_ULL(31, 27)
664 #define ERDMA_CEQE_HDR_PI_MASK GENMASK_ULL(55, 32)
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/linux-6.15/arch/x86/include/asm/
H A Dsev-common.h60 #define GHCB_MSR_AP_RESET_HOLD_RESULT_MASK GENMASK_ULL(51, 0)
65 #define GHCB_MSR_GPA_VALUE_MASK GENMASK_ULL(51, 0)
74 (((u64)((v) & GENMASK_ULL(51, 0)) << 12) | \
81 (((u64)(v) & GENMASK_ULL(63, 12)) >> 12)
100 ((u64)((gfn) & GENMASK_ULL(39, 0)) << 12) | \
105 #define GHCB_MSR_PSC_REQ_TO_OP(msr) (((msr) & GENMASK_ULL(55, 52)) >> 52)
110 (((u64)(val) & GENMASK_ULL(63, 32)) >> 32)
119 ((((u64)(v) & GENMASK_ULL(7, 0)) << 32) | \
126 (((u64)(v) & GENMASK_ULL(63, 32)) >> 32)
132 #define GHCB_MSR_HV_FT_MASK GENMASK_ULL(51, 0)
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/linux-6.15/drivers/gpu/drm/xe/regs/
H A Dxe_mchbar_regs.h22 #define PKG_TDP GENMASK_ULL(14, 0)
23 #define PKG_MIN_PWR GENMASK_ULL(30, 16)
24 #define PKG_MAX_PWR GENMASK_ULL(46, 32)
25 #define PKG_MAX_WIN GENMASK_ULL(54, 48)
26 #define PKG_MAX_WIN_X GENMASK_ULL(54, 53)
27 #define PKG_MAX_WIN_Y GENMASK_ULL(52, 48)
/linux-6.15/drivers/net/ethernet/intel/idpf/
H A Didpf_lan_txrx.h65 #define IDPF_TXD_COMPLQ_COMPL_TYPE_M GENMASK_ULL(13, 11)
67 #define IDPF_TXD_COMPLQ_QID_M GENMASK_ULL(9, 0)
96 #define IDPF_TXD_CTX_QW1_MSS_M GENMASK_ULL(63, 50)
98 #define IDPF_TXD_CTX_QW1_TSO_LEN_M GENMASK_ULL(47, 30)
100 #define IDPF_TXD_CTX_QW1_CMD_M GENMASK_ULL(15, 4)
102 #define IDPF_TXD_CTX_QW1_DTYPE_M GENMASK_ULL(3, 0)
104 #define IDPF_TXD_QW1_L2TAG1_M GENMASK_ULL(63, 48)
106 #define IDPF_TXD_QW1_TX_BUF_SZ_M GENMASK_ULL(47, 34)
108 #define IDPF_TXD_QW1_OFFSET_M GENMASK_ULL(33, 16)
110 #define IDPF_TXD_QW1_CMD_M GENMASK_ULL(15, 4)
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/linux-6.15/tools/testing/selftests/kvm/include/arm64/
H A Dgic_v3.h249 #define GICR_TYPER_AFFINITY GENMASK_ULL(63, 32)
251 #define GICR_INVLPIR_INTID GENMASK_ULL(31, 0)
252 #define GICR_INVLPIR_VPEID GENMASK_ULL(47, 32)
253 #define GICR_INVLPIR_V GENMASK_ULL(63, 63)
304 #define GICR_VPROPBASER_4_1_ADDR GENMASK_ULL(51, 12)
305 #define GICR_VPROPBASER_4_1_SIZE GENMASK_ULL(6, 0)
384 #define GITS_SGIR_VPEID GENMASK_ULL(47, 32)
385 #define GITS_SGIR_VINTID GENMASK_ULL(3, 0)
396 #define GITS_TYPER_ITT_ENTRY_SIZE GENMASK_ULL(7, 4)
399 #define GITS_TYPER_DEVBITS GENMASK_ULL(17, 13)
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/linux-6.15/include/linux/irqchip/
H A Darm-gic-v3.h249 #define GICR_TYPER_AFFINITY GENMASK_ULL(63, 32)
251 #define GICR_INVLPIR_INTID GENMASK_ULL(31, 0)
252 #define GICR_INVLPIR_VPEID GENMASK_ULL(47, 32)
253 #define GICR_INVLPIR_V GENMASK_ULL(63, 63)
304 #define GICR_VPROPBASER_4_1_ADDR GENMASK_ULL(51, 12)
305 #define GICR_VPROPBASER_4_1_SIZE GENMASK_ULL(6, 0)
384 #define GITS_SGIR_VPEID GENMASK_ULL(47, 32)
385 #define GITS_SGIR_VINTID GENMASK_ULL(3, 0)
396 #define GITS_TYPER_ITT_ENTRY_SIZE GENMASK_ULL(7, 4)
399 #define GITS_TYPER_DEVBITS GENMASK_ULL(17, 13)
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/linux-6.15/lib/tests/
H A Dtest_bits.c29 KUNIT_EXPECT_EQ(test, 1ull, GENMASK_ULL(0, 0)); in genmask_ull_test()
30 KUNIT_EXPECT_EQ(test, 3ull, GENMASK_ULL(1, 0)); in genmask_ull_test()
31 KUNIT_EXPECT_EQ(test, 0x000000ffffe00000ull, GENMASK_ULL(39, 21)); in genmask_ull_test()
32 KUNIT_EXPECT_EQ(test, 0xffffffffffffffffull, GENMASK_ULL(63, 0)); in genmask_ull_test()
36 GENMASK_ULL(0, 1); in genmask_ull_test()
37 GENMASK_ULL(0, 10); in genmask_ull_test()
38 GENMASK_ULL(9, 10); in genmask_ull_test()
/linux-6.15/drivers/net/ethernet/intel/ice/
H A Dice_parser.c302 #define ICE_IM_ALU_OPC GENMASK_ULL(5, 0)
489 #define ICE_MI_TSR GENMASK_ULL(7, 0)
490 #define ICE_MI_HO GENMASK_ULL(16, 8)
491 #define ICE_MI_PC GENMASK_ULL(24, 17)
492 #define ICE_MI_PGRN GENMASK_ULL(35, 25)
493 #define ICE_MI_CD GENMASK_ULL(38, 36)
495 #define ICE_MI_GADM GENMASK_ULL(44, 40)
496 #define ICE_MI_GADS GENMASK_ULL(48, 45)
497 #define ICE_MI_GADL GENMASK_ULL(53, 49)
498 #define ICE_MI_GAI GENMASK_ULL(59, 56)
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/linux-6.15/drivers/net/ethernet/intel/iavf/
H A Diavf_type.h206 #define IAVF_RXD_LEGACY_RSS_M GENMASK_ULL(63, 32)
208 #define IAVF_RXD_LEGACY_L2TAG1_M GENMASK_ULL(33, 16)
210 #define IAVF_RXD_FLEX_PTYPE_M GENMASK_ULL(25, 16)
212 #define IAVF_RXD_FLEX_PKT_LEN_M GENMASK_ULL(45, 32)
240 #define IAVF_RXD_LEGACY_FLTSTAT_M GENMASK_ULL(13, 12)
242 #define IAVF_RXD_LEGACY_PTYPE_M GENMASK_ULL(37, 30)
244 #define IAVF_RXD_LEGACY_LENGTH_M GENMASK_ULL(51, 38)
272 #define IAVF_RXD_FLEX_L2TAG1_M GENMASK_ULL(31, 16)
274 #define IAVF_RXD_FLEX_RSS_HASH_M GENMASK_ULL(63, 32)
280 #define IAVF_RXD_LEGACY_L2TAG2_M GENMASK_ULL(63, 32)
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/linux-6.15/drivers/gpu/drm/xe/
H A Dxe_hw_engine_types.h26 #define XE_HW_ENGINE_RCS_MASK GENMASK_ULL(XE_HW_ENGINE_RCS0, XE_HW_ENGINE_RCS0)
36 #define XE_HW_ENGINE_BCS_MASK GENMASK_ULL(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS0)
45 #define XE_HW_ENGINE_VCS_MASK GENMASK_ULL(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0)
50 #define XE_HW_ENGINE_VECS_MASK GENMASK_ULL(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0)
55 #define XE_HW_ENGINE_CCS_MASK GENMASK_ULL(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0)
57 #define XE_HW_ENGINE_GSCCS_MASK GENMASK_ULL(XE_HW_ENGINE_GSCCS0, XE_HW_ENGINE_GSCCS0)
/linux-6.15/drivers/ras/amd/atl/
H A Ddenormalize.c641 temp_addr_b = GENMASK_ULL(63, intlv_bit) & ctx->ret_addr; in denorm_addr_df3_6chan()
645 temp_addr_a = GENMASK_ULL(intlv_bit - 1, 0) & ctx->ret_addr; in denorm_addr_df3_6chan()
708 temp_addr_a &= GENMASK_ULL(13, 0); in denorm_addr_df4_np2()
712 temp_addr_b = GENMASK_ULL(63, shift_value) & ctx->ret_addr; in denorm_addr_df4_np2()
826 temp_addr_a = FIELD_GET(GENMASK_ULL(11, 10), addr) << 8; in normalize_addr_df4p5_np2()
835 temp_addr_a = FIELD_GET(GENMASK_ULL(11, 9), addr) << 8; in normalize_addr_df4p5_np2()
866 temp_addr_b = FIELD_GET(GENMASK_ULL(63, 12), addr) << 1; in normalize_addr_df4p5_np2()
880 temp_addr_b = FIELD_GET(GENMASK_ULL(63, 12), addr) << 2; in normalize_addr_df4p5_np2()
881 temp_addr_b |= FIELD_GET(GENMASK_ULL(9, 8), addr); in normalize_addr_df4p5_np2()
888 temp_addr_b = FIELD_GET(GENMASK_ULL(63, 12), addr) << 1; in normalize_addr_df4p5_np2()
[all …]
/linux-6.15/tools/include/linux/
H A Dcoresight-pmu.h60 #define CS_AUX_HW_ID_TRACE_ID_MASK GENMASK_ULL(7, 0)
61 #define CS_AUX_HW_ID_SINK_ID_MASK GENMASK_ULL(39, 8)
63 #define CS_AUX_HW_ID_MINOR_VERSION_MASK GENMASK_ULL(59, 56)
64 #define CS_AUX_HW_ID_MAJOR_VERSION_MASK GENMASK_ULL(63, 60)
/linux-6.15/include/linux/
H A Dcoresight-pmu.h60 #define CS_AUX_HW_ID_TRACE_ID_MASK GENMASK_ULL(7, 0)
61 #define CS_AUX_HW_ID_SINK_ID_MASK GENMASK_ULL(39, 8)
63 #define CS_AUX_HW_ID_MINOR_VERSION_MASK GENMASK_ULL(59, 56)
64 #define CS_AUX_HW_ID_MAJOR_VERSION_MASK GENMASK_ULL(63, 60)

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