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Searched refs:GENMASK (Results 1 – 25 of 2969) sorted by relevance

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/linux-6.15/include/soc/mscc/
H A Docelot_ana.h16 #define ANA_ANAGEFIL_PID_VAL_M GENMASK(18, 14)
20 #define ANA_ANAGEFIL_VID_VAL_M GENMASK(12, 0)
25 #define ANA_STORMLIMIT_CFG_STORM_RATE_M GENMASK(6, 3)
29 #define ANA_STORMLIMIT_CFG_STORM_MODE_M GENMASK(1, 0)
33 #define ANA_AUTOAGE_AGE_PERIOD_M GENMASK(20, 1)
41 #define ANA_AGENCTRL_FID_MASK_M GENMASK(23, 12)
62 #define ANA_FLOODING_FLD_BROADCAST_M GENMASK(11, 6)
65 #define ANA_FLOODING_FLD_MULTICAST_M GENMASK(5, 0)
74 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_M GENMASK(11, 6)
77 #define ANA_FLOODING_IPMC_FLD_MC6_DATA_M GENMASK(5, 0)
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H A Docelot_hsio.h91 #define HSIO_PLL5G_CFG0_SELBGV820_M GENMASK(26, 23)
94 #define HSIO_PLL5G_CFG0_LOOP_BW_RES_M GENMASK(22, 18)
97 #define HSIO_PLL5G_CFG0_SELCPI_M GENMASK(17, 16)
104 #define HSIO_PLL5G_CFG0_CPU_CLK_DIV_M GENMASK(11, 6)
107 #define HSIO_PLL5G_CFG0_CORE_CLK_DIV_M GENMASK(5, 0)
115 #define HSIO_PLL5G_CFG1_RC_CTRL_DATA_M GENMASK(13, 6)
141 #define HSIO_PLL5G_CFG2_GAIN_TEST_M GENMASK(9, 5)
167 #define HSIO_PLL5G_CFG3_FBDIVSEL_M GENMASK(7, 0)
195 #define HSIO_PLL5G_CFG6_DDR_CLK_DIV_M GENMASK(5, 0)
202 #define HSIO_PLL5G_STATUS0_READBACK_DATA_M GENMASK(8, 1)
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H A Docelot_qsys.h26 #define QSYS_EEE_THRES_EEE_HIGH_BYTES_M GENMASK(15, 8)
29 #define QSYS_EEE_THRES_EEE_HIGH_FRAMES_M GENMASK(7, 0)
34 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_M GENMASK(12, 8)
37 #define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M GENMASK(7, 0)
42 #define QSYS_QMAP_SE_BASE_M GENMASK(12, 5)
45 #define QSYS_QMAP_SE_IDX_SEL_M GENMASK(4, 2)
48 #define QSYS_QMAP_SE_INP_SEL_M GENMASK(1, 0)
55 #define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT_M GENMASK(18, 9)
60 #define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT_M GENMASK(6, 0)
68 #define QSYS_RED_PROFILE_WM_RED_HIGH_M GENMASK(7, 0)
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H A Docelot_sys.h21 #define SYS_FRM_AGING_MAX_AGE_M GENMASK(19, 0)
24 #define SYS_STAT_CFG_STAT_CLEAR_SHOT_M GENMASK(16, 10)
27 #define SYS_STAT_CFG_STAT_VIEW_M GENMASK(9, 0)
41 #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_M GENMASK(21, 6)
44 #define SYS_TIMESTAMP_OFFSET_TIMESTAMP_OFFSET_M GENMASK(5, 0)
47 #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START_M GENMASK(17, 9)
50 #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_STOP_M GENMASK(8, 0)
75 #define SYS_MMGT_FAST_FREEVLD_M GENMASK(7, 4)
78 #define SYS_MMGT_FAST_RELVLD_M GENMASK(3, 0)
83 #define SYS_EVENTS_DIF_EV_DRX_M GENMASK(8, 6)
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H A Docelot_dev.h18 #define DEV_CLOCK_CFG_LINK_SPEED_M GENMASK(1, 0)
28 #define DEV_EEE_CFG_EEE_TIMER_AGE_M GENMASK(21, 15)
31 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_M GENMASK(14, 8)
34 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_M GENMASK(7, 1)
39 #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_M GENMASK(11, 4)
42 #define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG_M GENMASK(3, 0)
52 #define DEV_MAC_TAGS_CFG_TAG_ID_M GENMASK(31, 16)
63 #define DEV_MAC_IFG_CFG_TX_IFG_M GENMASK(12, 8)
66 #define DEV_MAC_IFG_CFG_RX_IFG2_M GENMASK(7, 4)
69 #define DEV_MAC_IFG_CFG_RX_IFG1_M GENMASK(3, 0)
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/linux-6.15/drivers/net/wireless/mediatek/mt76/
H A Dmt76_connac3_mac.h24 #define MT_RXD0_LENGTH GENMASK(15, 0)
26 #define MT_RXD0_PKT_TYPE GENMASK(31, 27)
105 #define MT_PRXV_NSTS GENMASK(10, 7)
111 #define MT_PRXV_RCPI1 GENMASK(15, 8)
112 #define MT_PRXV_RCPI0 GENMASK(7, 0)
139 #define MT_CRXV_HE_RU0 GENMASK(8, 0)
223 #define MT_TXD1_TID GENMASK(24, 21)
267 #define MT_TXD5_PID GENMASK(7, 0)
272 #define MT_TXD6_BW GENMASK(24, 22)
320 #define MT_TXS0_BW GENMASK(31, 29)
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H A Dmt76_connac2_mac.h42 #define MT_TX_FREE_COUNT GENMASK(12, 0)
48 #define MT_TX_FREE_RATE GENMASK(13, 0)
50 #define MT_TXD0_Q_IDX GENMASK(31, 25)
59 #define MT_TXD1_TID GENMASK(22, 20)
65 #define MT_TXD1_WLAN_IDX GENMASK(9, 0)
71 #define MT_TXD2_FRAG GENMASK(15, 14)
87 #define MT_TXD3_SEQ GENMASK(27, 16)
105 #define MT_TXD5_PID GENMASK(7, 0)
110 #define MT_TXD6_SGI GENMASK(15, 14)
117 #define MT_TXD6_BW GENMASK(1, 0)
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H A Dmt76x02_regs.h19 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
20 #define MT_EFUSE_CTRL_MODE GENMASK(7, 6)
23 #define MT_EFUSE_CTRL_AIN GENMASK(25, 16)
68 #define MT_XO_CTRL5_C2_VAL GENMASK(14, 8)
110 #define MT_INT_RX_DONE_ALL GENMASK(1, 0)
142 #define MT_WMM_AIFSN_MASK GENMASK(3, 0)
146 #define MT_WMM_CWMIN_MASK GENMASK(3, 0)
150 #define MT_WMM_CWMAX_MASK GENMASK(3, 0)
156 #define MT_WMM_TXOP_MASK GENMASK(15, 0)
167 #define MT_US_CYC_CNT GENMASK(7, 0)
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/linux-6.15/drivers/net/wireless/realtek/rtw89/
H A Dtxrx.h10 #define DATA_RATE_MODE_CTRL_MASK GENMASK(8, 7)
12 #define DATA_RATE_NOT_HT_IDX_MASK GENMASK(3, 0)
14 #define DATA_RATE_HT_IDX_MASK GENMASK(4, 0)
15 #define DATA_RATE_HT_IDX_MASK_V1 GENMASK(4, 0)
17 #define DATA_RATE_HT_NSS_MASK GENMASK(4, 3)
20 #define DATA_RATE_NSS_MASK_V1 GENMASK(7, 5)
21 #define DATA_RATE_MCS_MASK_V1 GENMASK(4, 0)
345 #define AX_RXD_BW_MASK GENMASK(31, 30)
374 #define AX_RXD_TYPE_MASK GENMASK(1, 0)
381 #define AX_RXD_TID_MASK GENMASK(11, 8)
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H A Dcam.h12 #define RTW89_BSSID_MATCH_ALL GENMASK(5, 0)
13 #define RTW89_BSSID_MATCH_5_BYTES GENMASK(4, 0)
382 #define DCTLINFO_V1_W0_ALL GENMASK(31, 0)
384 #define DCTLINFO_V1_W1_ALL GENMASK(31, 0)
391 #define DCTLINFO_V1_W2_ALL GENMASK(29, 0)
397 #define DCTLINFO_V1_W3_ALL GENMASK(31, 0)
412 #define DCTLINFO_V1_W4_ALL (GENMASK(31, 15) | GENMASK(10, 0))
417 #define DCTLINFO_V1_W5_ALL GENMASK(31, 0)
422 #define DCTLINFO_V1_W6_ALL GENMASK(31, 0)
467 #define DCTLINFO_V2_W0_ALL GENMASK(31, 0)
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H A Dreg.h12 #define B_AX_PWC_EV2EF_MASK GENMASK(15, 14)
108 #define B_AX_DBG_SEL0 GENMASK(7, 0)
137 #define B_AX_R_AX_BG GENMASK(1, 0)
216 #define PS_CPWM_STATE GENMASK(2, 0)
8346 #define B_TIA0_A GENMASK(7, 0)
8366 #define B_DCFO GENMASK(7, 0)
8405 #define B_LNA6 GENMASK(31, 24)
8409 #define B_TIA0_B GENMASK(7, 0)
8883 #define B_FC0 GENMASK(12, 0)
9269 #define B_ADDCK0 GENMASK(9, 8)
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H A Dfw.h702 GENMASK(8, 0)); in SET_CMC_TBL_DATARATE()
800 GENMASK(8, 0)); in SET_CMC_TBL_DATA_RTY_LOWEST_RATE()
856 GENMASK(5, 0)); in SET_CMC_TBL_DATA_TX_CNT_LMT()
933 GENMASK(7, 0)); in SET_CMC_TBL_MAX_AGG_NUM()
940 GENMASK(9, 8)); in SET_CMC_TBL_BA_BMAP()
982 GENMASK(2, 0)); in SET_CMC_TBL_MULTI_PORT_ID()
996 GENMASK(7, 4)); in SET_CMC_TBL_MBSSID()
1411 #define CCTLINFO_G7_W0_ALL (GENMASK(31, 20) | GENMASK(18, 0))
1455 #define CCTLINFO_G7_W4_ALL (GENMASK(31, 14) | GENMASK(12, 0))
1464 #define CCTLINFO_G7_W5_ALL (GENMASK(31, 16) | GENMASK(14, 0))
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/linux-6.15/drivers/phy/
H A Dphy-airoha-pcie-regs.h13 #define CSR_2L_PXP_CMN_TRIM_MASK GENMASK(28, 24)
21 #define CSR_2L_PXP_JCPLL_LPF_BR GENMASK(4, 0)
22 #define CSR_2L_PXP_JCPLL_LPF_BC GENMASK(12, 8)
23 #define CSR_2L_PXP_JCPLL_LPF_BP GENMASK(20, 16)
24 #define CSR_2L_PXP_JCPLL_LPF_BWR GENMASK(28, 24)
27 #define CSR_2L_PXP_JCPLL_LPF_BWC GENMASK(4, 0)
33 #define CSR_2L_PXP_JCPLL_KBAND_KF GENMASK(9, 8)
46 #define CSR_2L_PXP_JCPLL_RST_DLY GENMASK(2, 0)
340 #define PCIE_LOCK_LOCKTH GENMASK(11, 8)
345 #define PCIE_CAL_OUT_OS GENMASK(11, 8)
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/linux-6.15/drivers/net/wireless/mediatek/mt76/mt7603/
H A Dmac.h6 #define MT_RXD0_LENGTH GENMASK(15, 0)
7 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
94 #define MT_RXV3_RCPI0 GENMASK(15, 8)
109 #define MT_RXV5_FOE GENMASK(18, 7)
117 #define MT_RXV6_NF2 GENMASK(23, 16)
118 #define MT_RXV6_NF1 GENMASK(15, 8)
119 #define MT_RXV6_NF0 GENMASK(7, 0)
141 #define MT_TXD1_TID GENMASK(22, 20)
181 #define MT_TXD5_PID GENMASK(7, 0)
192 #define MT_TXD6_BW GENMASK(9, 8)
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H A Dregs.h29 #define MT_INT_RX_DONE_ALL GENMASK(1, 0)
30 #define MT_INT_TX_DONE_ALL GENMASK(19, 4)
108 #define MT_PSE_FRP_P0 GENMASK(2, 0)
109 #define MT_PSE_FRP_P1 GENMASK(5, 3)
143 #define MT_AGC_41_RSSI_1 GENMASK(7, 0)
148 #define MT_RXTD_6_ACI_TH GENMASK(4, 0)
229 #define MT_AGG_BWCR_BW GENMASK(3, 2)
395 #define MT_IFS_EIFS GENMASK(8, 0)
396 #define MT_IFS_RIFS GENMASK(14, 10)
397 #define MT_IFS_SIFS GENMASK(22, 16)
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/linux-6.15/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dmac.h10 #define MT_RXD0_LENGTH GENMASK(15, 0)
12 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
107 #define MT_RXV4_RCPI0 GENMASK(7, 0)
109 #define MT_RXV5_FOE GENMASK(11, 0)
111 #define MT_RXV6_NF3 GENMASK(31, 24)
112 #define MT_RXV6_NF2 GENMASK(23, 16)
113 #define MT_RXV6_NF1 GENMASK(15, 8)
114 #define MT_RXV6_NF0 GENMASK(7, 0)
208 #define MT_TXD5_PID GENMASK(7, 0)
218 #define MT_TXD6_BW GENMASK(1, 0)
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/linux-6.15/drivers/ras/amd/atl/
H A Dreg_fields.h37 #define DF2_COH_ST_FABRIC_ID GENMASK(19, 8)
82 #define DF2_DST_FABRIC_ID GENMASK(7, 0)
83 #define DF3_DST_FABRIC_ID GENMASK(9, 0)
85 #define DF4_DST_FABRIC_ID GENMASK(27, 16)
109 #define DF2_DIE_ID_MASK GENMASK(15, 8)
110 #define DF3_DIE_ID_MASK GENMASK(18, 16)
111 #define DF4_DIE_ID_MASK GENMASK(15, 0)
129 #define DF2_DIE_ID_SHIFT GENMASK(27, 24)
171 #define DF2_BASE_ADDR GENMASK(31, 12)
172 #define DF4_BASE_ADDR GENMASK(27, 0)
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/linux-6.15/drivers/hid/intel-thc-hid/intel-thc/
H A Dintel-thc-hw.h271 #define THC_CFG_CC_RID_RID GENMASK(7, 0)
272 #define THC_CFG_CC_RID_PI GENMASK(15, 8)
273 #define THC_CFG_CC_RID_SCC GENMASK(23, 16)
274 #define THC_CFG_CC_RID_BCC GENMASK(31, 24)
291 #define THC_CFG_CAPP_CP GENMASK(7, 0)
293 #define THC_CFG_INT_ILINE GENMASK(7, 0)
294 #define THC_CFG_INT_IPIN GENMASK(15, 8)
309 #define THC_CFG_MSIMD_MDAT GENMASK(15, 0)
354 #define THC_CFG_MANID_PROC GENMASK(7, 0)
355 #define THC_CFG_MANID_MID GENMASK(15, 8)
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/linux-6.15/drivers/net/ethernet/mediatek/
H A Dmtk_wed_regs.h8 #define MTK_WDMA_DESC_CTRL_LEN1 GENMASK(14, 0)
9 #define MTK_WDMA_DESC_CTRL_LEN1_V2 GENMASK(13, 0)
12 #define MTK_WDMA_DESC_CTRL_LEN0 GENMASK(29, 16)
109 #define MTK_WED_STATUS_TX GENMASK(15, 8)
123 #define MTK_WED_TX_BM_SW_TAIL_IDX GENMASK(16, 0)
126 #define MTK_WED_TX_BM_TKID_START GENMASK(15, 0)
127 #define MTK_WED_TX_BM_TKID_END GENMASK(31, 16)
132 #define MTK_WED_TX_BM_INTF_TKID GENMASK(15, 0)
138 #define MTK_WED_TX_BM_DYN_THR_LO GENMASK(6, 0)
414 #define MTK_WED_RX_BM_SW_TAIL GENMASK(15, 0)
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/linux-6.15/drivers/media/platform/ti/cal/
H A Dcal_regs.h100 #define CAL_HL_HWINFO_WFIFO_MASK GENMASK(3, 0)
101 #define CAL_HL_HWINFO_RFIFO_MASK GENMASK(7, 4)
102 #define CAL_HL_HWINFO_PCTX_MASK GENMASK(12, 8)
149 #define CAL_PIX_PROC_DPCMD_MASK GENMASK(9, 5)
185 #define CAL_CTRL_TAGCNT_MASK GENMASK(4, 1)
192 #define CAL_CTRL_MFLAGL_MASK GENMASK(20, 13)
197 #define CAL_CTRL_MFLAGH_MASK GENMASK(31, 24)
317 #define CAL_WR_DMA_ADDR_MASK GENMASK(31, 4)
319 #define CAL_WR_DMA_OFST_MASK GENMASK(18, 4)
416 #define CAL_CSI2_CTX_DT_MASK GENMASK(5, 0)
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/linux-6.15/drivers/net/can/ctucanfd/
H A Dctucanfd_kregs.h115 #define REG_MODE_RTRTH GENMASK(20, 17)
171 #define REG_BTR_PROP GENMASK(6, 0)
172 #define REG_BTR_PH1 GENMASK(12, 7)
173 #define REG_BTR_PH2 GENMASK(18, 13)
174 #define REG_BTR_BRP GENMASK(26, 19)
175 #define REG_BTR_SJW GENMASK(31, 27)
178 #define REG_BTR_FD_PROP_FD GENMASK(5, 0)
185 #define REG_EWL_EW_LIMIT GENMASK(7, 0)
192 #define REG_REC_REC_VAL GENMASK(8, 0)
193 #define REG_REC_TEC_VAL GENMASK(24, 16)
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/linux-6.15/drivers/gpu/drm/mediatek/
H A Dmtk_dp_reg.h17 #define RG_XTP_GLB_BIAS_INTR_CTRL GENMASK(20, 16)
19 #define RG_CKM_PT0_CKTX_IMPSEL GENMASK(23, 20)
56 #define DP_PWR_STATE_MASK GENMASK(1, 0)
61 #define DP_TX0_VOLT_SWING_MASK GENMASK(1, 0)
63 #define DP_TX0_PRE_EMPH_MASK GENMASK(3, 2)
65 #define DP_TX1_VOLT_SWING_MASK GENMASK(9, 8)
67 #define DP_TX1_PRE_EMPH_MASK GENMASK(11, 10)
68 #define DP_TX2_VOLT_SWING_MASK GENMASK(17, 16)
69 #define DP_TX2_PRE_EMPH_MASK GENMASK(19, 18)
70 #define DP_TX3_VOLT_SWING_MASK GENMASK(25, 24)
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/linux-6.15/drivers/net/wireless/ath/ath12k/
H A Dhal_desc.h11 #define BUFFER_ADDR_INFO0_ADDR GENMASK(31, 0)
13 #define BUFFER_ADDR_INFO1_ADDR GENMASK(7, 0)
14 #define BUFFER_ADDR_INFO1_RET_BUF_MGR GENMASK(11, 8)
15 #define BUFFER_ADDR_INFO1_SW_COOKIE GENMASK(31, 12)
569 #define HAL_TLV_HDR_TAG GENMASK(9, 1)
570 #define HAL_TLV_HDR_LEN GENMASK(25, 10)
571 #define HAL_TLV_USR_ID GENMASK(31, 26)
580 #define HAL_TLV_64_HDR_TAG GENMASK(9, 1)
581 #define HAL_TLV_64_HDR_LEN GENMASK(21, 10)
582 #define HAL_TLV_64_USR_ID GENMASK(31, 26)
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/linux-6.15/drivers/net/ipa/reg/
H A Dipa_reg-v5.0.c13 [MAX_PIPES] = GENMASK(7, 0),
14 [MAX_CONS_PIPES] = GENMASK(15, 8),
15 [MAX_PROD_PIPES] = GENMASK(23, 16),
16 [PROD_LOWEST] = GENMASK(31, 24),
102 [MEM_SIZE] = GENMASK(15, 0),
185 [DIV_VALUE] = GENMASK(8, 0),
203 [X_MIN_LIM] = GENMASK(5, 0),
217 [X_MIN_LIM] = GENMASK(5, 0),
330 [NAT_EN] = GENMASK(1, 0),
337 [HDR_LEN] = GENMASK(5, 0),
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H A Dipa_reg-v5.5.c13 [MAX_PIPES] = GENMASK(7, 0),
14 [MAX_CONS_PIPES] = GENMASK(15, 8),
15 [MAX_PROD_PIPES] = GENMASK(23, 16),
16 [PROD_LOWEST] = GENMASK(31, 24),
101 [MEM_SIZE] = GENMASK(15, 0),
182 [DIV_VALUE] = GENMASK(8, 0),
200 [X_MIN_LIM] = GENMASK(5, 0),
214 [X_MIN_LIM] = GENMASK(5, 0),
328 [NAT_EN] = GENMASK(1, 0),
335 [HDR_LEN] = GENMASK(5, 0),
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