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Searched refs:GEN8_MASTER_IRQ (Results 1 – 5 of 5) sorted by relevance

/linux-6.15/drivers/gpu/drm/i915/
H A Di915_irq.c343 master_ctl = intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; in cherryview_irq_handler()
364 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0); in cherryview_irq_handler()
392 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); in cherryview_irq_handler()
490 raw_reg_write(regs, GEN8_MASTER_IRQ, 0); in gen8_master_intr_disable()
498 return raw_reg_read(regs, GEN8_MASTER_IRQ); in gen8_master_intr_disable()
503 raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); in gen8_master_intr_enable()
756 intel_uncore_write(uncore, GEN8_MASTER_IRQ, 0); in cherryview_irq_reset()
757 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ); in cherryview_irq_reset()
836 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); in cherryview_irq_postinstall()
837 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ); in cherryview_irq_postinstall()
H A Dintel_gvt_mmio_table.c780 MMIO_D(GEN8_MASTER_IRQ); in iterate_bdw_plus_mmio()
H A Di915_reg.h2133 #define GEN8_MASTER_IRQ _MMIO(0x44200) macro
/linux-6.15/drivers/gpu/drm/i915/gvt/
H A Dinterrupt.c513 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(master, GEN8_MASTER_IRQ);
527 if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) & in gen8_check_pending_irq()
544 if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) in gen8_check_pending_irq()
H A Dhandlers.c2517 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, in init_bdw_mmio_info()