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Searched refs:GEN8_L3SQCREG4 (Results 1 – 6 of 6) sorted by relevance

/linux-6.15/drivers/gpu/drm/i915/gt/
H A Dintel_workarounds.c1907 whitelist_mcr_reg(w, GEN8_L3SQCREG4); in skl_whitelist_build()
1928 whitelist_mcr_reg(w, GEN8_L3SQCREG4); in kbl_whitelist_build()
2350 GEN8_L3SQCREG4, in rcs_engine_wa_init()
2479 GEN8_L3SQCREG4, in rcs_engine_wa_init()
2485 wa_mcr_write_clr_set(wal, GEN8_L3SQCREG4, in rcs_engine_wa_init()
H A Dintel_lrc.c1642 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
1648 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
1657 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
H A Dintel_gt_regs.h992 #define GEN8_L3SQCREG4 MCR_REG(0xb118) macro
/linux-6.15/drivers/gpu/drm/i915/
H A Dintel_gvt_mmio_table.c840 MMIO_D(GEN8_L3SQCREG4); in iterate_bdw_plus_mmio()
/linux-6.15/drivers/gpu/drm/i915/gvt/
H A Dcmd_parser.c924 if (offset == i915_mmio_reg_offset(GEN8_L3SQCREG4) || in cmd_reg_handler()
H A Dhandlers.c2568 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()