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Searched refs:GDS_GWS_VMID0__SIZE__SHIFT (Results 1 – 19 of 19) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v7_0.c4032 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); in gfx_v7_0_ring_emit_gds_switch()
H A Dgfx_v9_4_3.c2459 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); in gfx_v9_4_3_ring_emit_gds_switch()
H A Dgfx_v8_0.c5165 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); in gfx_v8_0_ring_emit_gds_switch()
H A Dgfx_v11_0.c5050 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); in gfx_v11_0_ring_emit_gds_switch()
H A Dgfx_v9_0.c4307 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); in gfx_v9_0_ring_emit_gds_switch()
H A Dgfx_v10_0.c7746 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); in gfx_v10_0_ring_emit_gds_switch()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h15088 #define GDS_GWS_VMID0__SIZE__SHIFT 0x10 macro
H A Dgfx_8_0_sh_mask.h17048 #define GDS_GWS_VMID0__SIZE__SHIFT 0x10 macro
H A Dgfx_8_1_sh_mask.h17636 #define GDS_GWS_VMID0__SIZE__SHIFT 0x10 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h13663 #define GDS_GWS_VMID0__SIZE__SHIFT … macro
H A Dgc_9_1_sh_mask.h14966 #define GDS_GWS_VMID0__SIZE__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h14824 #define GDS_GWS_VMID0__SIZE__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h17129 #define GDS_GWS_VMID0__SIZE__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h7166 #define GDS_GWS_VMID0__SIZE__SHIFT … macro
H A Dgc_11_5_0_sh_mask.h14701 #define GDS_GWS_VMID0__SIZE__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h18007 #define GDS_GWS_VMID0__SIZE__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h21207 #define GDS_GWS_VMID0__SIZE__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h20252 #define GDS_GWS_VMID0__SIZE__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h19300 #define GDS_GWS_VMID0__SIZE__SHIFT … macro