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Searched refs:GCR (Results 1 – 16 of 16) sorted by relevance

/linux-6.15/sound/arm/
H A Dpxa2xx-ac97-lib.c127 writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR); in pxa_ac97_warm_pxa25x()
133 writel(readl(ac97_reg_base + GCR) & (~GCR_COLD_RST), ac97_reg_base + GCR); /* then assert nCRST */ in pxa_ac97_cold_pxa25x()
149 writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR); in pxa_ac97_warm_pxa27x()
175 writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR); in pxa_ac97_warm_pxa3xx()
181 writel(0, ac97_reg_base + GCR); in pxa_ac97_cold_pxa3xx()
184 writel(0, ac97_reg_base + GCR); in pxa_ac97_cold_pxa3xx()
192 writel(readl(ac97_reg_base + GCR) & (~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN)), ac97_reg_base + GCR); in pxa_ac97_cold_pxa3xx()
278 writel(gcr, ac97_reg_base + GCR); in pxa2xx_ac97_finish_reset()
310 writel(readl(ac97_reg_base + GCR) | (GCR_ACLINK_OFF), ac97_reg_base + GCR); in pxa2xx_ac97_hw_suspend()
415 writel(readl(ac97_reg_base + GCR) | (GCR_ACLINK_OFF), ac97_reg_base + GCR); in pxa2xx_ac97_hw_probe()
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H A Dpxa2xx-ac97-regs.h21 #define GCR (0x000C) /* Global Control Register */ macro
/linux-6.15/drivers/gpu/drm/stm/
H A Dlvds.c176 u32 GCR; /* Global Control Register */ member
206 .GCR = 0x0,
232 .GCR = 0x0,
363 lvds_set(lvds, phy->base + phy->ofs.GCR, lvds_gcr); in lvds_pll_enable()
573 lvds_set(lvds, phy->base + phy->ofs.GCR, PHY_GCR_DIV_RSTN | PHY_GCR_RSTZ); in lvds_pixel_clk_enable()
587 lvds_set(lvds, phy->base + phy->ofs.GCR, PHY_GCR_DIV_RSTN | PHY_GCR_RSTZ); in lvds_pixel_clk_enable()
612 lvds_clear(lvds, lvds->primary->base + lvds->primary->ofs.GCR, in lvds_pixel_clk_disable()
616 lvds_clear(lvds, lvds->primary->base + lvds->primary->ofs.GCR, in lvds_pixel_clk_disable()
621 lvds_clear(lvds, lvds->secondary->base + lvds->secondary->ofs.GCR, in lvds_pixel_clk_disable()
625 lvds_clear(lvds, lvds->secondary->base + lvds->secondary->ofs.GCR, in lvds_pixel_clk_disable()
/linux-6.15/Documentation/devicetree/bindings/soc/nuvoton/
H A Dnuvoton,npcm-gcr.yaml14 The Global Control Registers (GCR) are a block of registers in Nuvoton SoCs
/linux-6.15/arch/arm/mach-omap2/
H A Ddma.c37 [GCR] = { 0x0078, 0x00, OMAP_DMA_REG_32BIT },
/linux-6.15/Documentation/devicetree/bindings/reset/
H A Dnuvoton,npcm750-reset.yaml33 description: a phandle to access GCR registers.
/linux-6.15/Documentation/devicetree/bindings/media/
H A Dnuvoton,npcm-vcd.yaml33 description: phandle to access GCR (Global Control Register) registers.
/linux-6.15/Documentation/devicetree/bindings/mmc/
H A Dnuvoton,ma35d1-sdhci.yaml50 description: phandle to access GCR (Global Control Register) registers.
/linux-6.15/drivers/net/ethernet/intel/e1000e/
H A D82571.c1114 reg_data = er32(GCR); in e1000_init_hw_82571()
1116 ew32(GCR, reg_data); in e1000_init_hw_82571()
1246 reg = er32(GCR); in e1000_initialize_hw_bits_82571()
1248 ew32(GCR, reg); in e1000_initialize_hw_bits_82571()
H A Dmac.c1690 gcr = er32(GCR); in e1000e_set_pcie_no_snoop()
1693 ew32(GCR, gcr); in e1000e_set_pcie_no_snoop()
/linux-6.15/include/linux/
H A Domap-dma.h140 GCR, GSCR, GRST1, HW_ID, enumerator
/linux-6.15/arch/arm/mach-omap1/
H A Ddma.c36 [GCR] = { 0x0400, 0x00, OMAP_DMA_REG_16BIT },
/linux-6.15/Documentation/devicetree/bindings/pinctrl/
H A Dnuvoton,npcm845-pinctrl.yaml33 description: a phandle to access GCR registers.
/linux-6.15/drivers/net/ethernet/via/
H A Dvia-velocity.c3082 u8 GCR; in velocity_set_wol() local
3083 GCR = readb(&regs->CHIPGCR); in velocity_set_wol()
3084 GCR = (GCR & ~CHIPGCR_FCGMII) | CHIPGCR_FCFDX; in velocity_set_wol()
3085 writeb(GCR, &regs->CHIPGCR); in velocity_set_wol()
/linux-6.15/drivers/dma/ti/
H A Domap-dma.c1580 od->context.gcr = omap_dma_glbl_read(od, GCR); in omap_dma_context_save()
1587 omap_dma_glbl_write(od, GCR, od->context.gcr); in omap_dma_context_restore()
1643 omap_dma_glbl_write(od, GCR, val); in omap_dma_init_gcr()
/linux-6.15/drivers/tty/serial/
H A Dfsl_linflexuart.c41 #define GCR 0x004C /* Global control register */ macro