Searched refs:FW_BLC_SELF_EN (Results 1 – 5 of 5) sorted by relevance
472 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) { in cdv_disable_sr()475 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); in cdv_disable_sr()535 REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); in cdv_update_wm()
567 #define FW_BLC_SELF_EN (1<<15) macro
159 was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN; in _intel_set_memory_cxsr()160 intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); in _intel_set_memory_cxsr()172 was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN; in _intel_set_memory_cxsr()173 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : in _intel_set_memory_cxsr()174 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); in _intel_set_memory_cxsr()3769 wm->cxsr = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN; in g4x_wm_get_hw_state()
96 sr_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN; in i915_sr_status()
505 #define FW_BLC_SELF_EN (1 << 15) /* 945 only */ macro