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/linux-6.15/drivers/staging/axis-fifo/
H A DKconfig3 # "Xilinx AXI-Stream FIFO IP core driver"
6 tristate "Xilinx AXI-Stream FIFO IP core driver"
9 This adds support for the Xilinx AXI-Stream FIFO IP core driver.
10 The AXI Streaming FIFO allows memory mapped access to a AXI Streaming
11 interface. The Xilinx AXI-Stream FIFO IP core can be used to interface
H A Daxis-fifo.txt1 Xilinx AXI-Stream FIFO v4.1 IP core
37 - xlnx,rx-fifo-depth: Depth of RX FIFO in words
45 - xlnx,tx-fifo-depth: Depth of TX FIFO in words
51 - xlnx,use-rx-data: <0x1> if RX FIFO is enabled, <0x0> otherwise
54 - xlnx,use-tx-data: <0x1> if TX FIFO is enabled, <0x0> otherwise
/linux-6.15/Documentation/devicetree/bindings/interrupt-controller/
H A Dcirrus,clps711x-intc.txt24 12: UTXINT1 UART1 transmit FIFO half empty
25 13: URXINT1 UART1 receive FIFO half full
29 17: SS2RX SSI2 receive FIFO half or greater full
30 18: SS2TX SSI2 transmit FIFO less than half empty
31 28: UTXINT2 UART2 transmit FIFO half empty
32 29: URXINT2 UART2 receive FIFO half full
/linux-6.15/Documentation/translations/zh_CN/security/tpm/
H A Dtpm_tis.rst9 TPM FIFO接口驱动
12 TCG PTP规范定义了两种接口类型：FIFO和CRB。前者基于顺序的读写操作，
15 FIFO（先进先出）接口被tpm_tis_core依赖的驱动程序使用。最初，Linux只
19 由于历史原因，最初的MMIO驱动被称为tpm_tis，而FIFO驱动的框架被命名为
/linux-6.15/Documentation/devicetree/bindings/display/bridge/
H A Dsil,sii9022.yaml63 Each integer indicates which I2S pin is connected to which audio FIFO.
64 The first integer selects the I2S audio pin for the first audio FIFO#0
65 (HDMI channels 1&2), the second for FIFO#1 (HDMI channels 3&4), and so
67 connected to any FIFO, but there can be no gaps. E.g. an I2S pin must be
68 mapped to FIFO#0 and FIFO#1 before mapping a channel to FIFO#2. The
70 FIFO#0.
/linux-6.15/Documentation/networking/device_drivers/can/freescale/
H A Dflexcan.rst15 - FIFO
20 configured for RX-FIFO mode.
22 The RX FIFO mode uses a hardware FIFO with a depth of 6 CAN frames,
23 while the mailbox mode uses a software FIFO with a depth of up to 62
40 more performant "RX mailbox" mode and will use "RX FIFO" mode
/linux-6.15/Documentation/devicetree/bindings/net/can/
H A Dbosch,m_can.yaml57 and each element(e.g Rx FIFO or Tx Buffer and etc) number
67 are used to specify how many elements are used for each FIFO/Buffer.
72 Rx FIFO 0 0-64 elements / 0-1152 words
73 Rx FIFO 1 0-64 elements / 0-1152 words
75 Tx Event FIFO 0-32 elements / 0-64 words
92 - description: Rx FIFO 0 0-64 elements / 0-1152 words
95 - description: Rx FIFO 1 0-64 elements / 0-1152 words
101 - description: Tx Event FIFO 0-32 elements / 0-64 words
H A Dti,tcan4x5x.yaml56 and each element(e.g Rx FIFO or Tx Buffer and etc) number
66 are used to specify how many elements are used for each FIFO/Buffer.
71 Rx FIFO 0 0-64 elements / 0-1152 words
72 Rx FIFO 1 0-64 elements / 0-1152 words
74 Tx Event FIFO 0-32 elements / 0-64 words
91 - description: Rx FIFO 0 0-64 elements / 0-1152 words
94 - description: Rx FIFO 1 0-64 elements / 0-1152 words
100 - description: Tx Event FIFO 0-32 elements / 0-64 words
/linux-6.15/Documentation/devicetree/bindings/dma/stm32/
H A Dst,stm32-dma.yaml34 -bit 0-1: DMA FIFO threshold selection
35 0x0: 1/4 full FIFO
36 0x1: 1/2 full FIFO
37 0x2: 3/4 full FIFO
38 0x3: full FIFO
40 0x0: FIFO mode with threshold selectable with bit 0-1
42 from/to the memory, FIFO is bypassed.
H A Dst,stm32-dma3.yaml66 -bit 4-7: The FIFO requirement for queuing source/destination transfers
67 0x0: no FIFO requirement/any channel can fit
68 0x2: FIFO of 8 bytes (2^2+1)
69 0x4: FIFO of 32 bytes (2^4+1)
70 0x6: FIFO of 128 bytes (2^6+1)
71 0x7: FIFO of 256 bytes (2^7+1)
/linux-6.15/Documentation/accel/qaic/
H A Daic100.rst248 FIFO is the request FIFO. The other FIFO is the response FIFO.
253 latest item in the FIFO the device has consumed.
255 increments this register to add new items to the FIFO.
257 the latest item in the FIFO the host has consumed.
259 increments this register to add new items to the FIFO.
262 FIFO element pointed to by the register: FIFO base address + register * element
275 Request FIFO
278 A request FIFO element has the following structure:
305 request ID. A request FIFO element and a response FIFO element with
391 Response FIFO
[all …]
/linux-6.15/drivers/video/fbdev/riva/
H A Driva_hw.c1351 LOAD_FIXED_STATE(nv4,FIFO); in UpdateFifoState()
1362 LOAD_FIXED_STATE(nv10,FIFO); in UpdateFifoState()
1645 LOAD_FIXED_STATE(Riva,FIFO); in LoadStateExt()
1841 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); in nv3SetSurfaces2D()
1844 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); in nv3SetSurfaces2D()
1846 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); in nv3SetSurfaces2D()
1848 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013); in nv3SetSurfaces2D()
1858 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); in nv4SetSurfaces2D()
1860 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); in nv4SetSurfaces2D()
1862 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); in nv4SetSurfaces2D()
[all …]
/linux-6.15/Documentation/devicetree/bindings/mailbox/
H A Darm,mhuv3.yaml83 - FIFO Extension (FE): FE defines a Channel type called a FIFO Channel (FFCH).
87 FIFO has room for the Transfer.
98 memory region, wherein the MHU FIFO is used to transmit, in order, a small
142 description: PBX/MBX FIFO Combined interrupt
144 description: PBX/MBX FIFO Channel <N> Low Tide interrupt
146 description: PBX/MBX FIFO Channel <N> High Tide interrupt
148 description: PBX/MBX FIFO Channel <N> Flush interrupt
156 description: MBX FIFO Channel <N> Transfer interrupt
160 description: PBX FIFO Channel <N> Transfer Ack interrupt
179 mboxes = <&mhu FE_EXT 1 0>; // FE, FIFO Channel Window 1.
[all …]
/linux-6.15/Documentation/devicetree/bindings/serial/
H A Dmvebu-uart.txt7 (32 bytes FIFO, no DMA, level interrupts, 8-bit access to the
8 FIFO), called also UART1.
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
11 accesses to the FIFO), called also UART2.
/linux-6.15/Documentation/security/tpm/
H A Dtpm_tis.rst4 TPM FIFO interface driver
7 TCG PTP Specification defines two interface types: FIFO and CRB. The former is
11 FIFO (First-In-First-Out) interface is used by the tpm_tis_core dependent
17 framework for FIFO drivers is named as tpm_tis_core. The postfix "tis" in
/linux-6.15/Documentation/devicetree/bindings/powerpc/fsl/
H A Dmpc5121-psc.txt8 fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
19 PSC FIFO Controller and b is a field that represents an
42 FIFO Controller
44 PSC FIFO Controller and b is a field that represents an
/linux-6.15/Documentation/devicetree/bindings/sound/
H A Dsamsung-i2s.yaml22 secondary FIFO, s/w reset control and internal mux for root clock
26 playback, stereo channel capture, secondary FIFO using internal
33 Exynos7 I2S has 7.1 channel TDM support for capture, secondary FIFO
42 capture, secondary FIFO using external DMA, s/w reset control,
H A Ddavinci-mcasp-audio.yaml83 0 disables the FIFO use
84 if property is missing, then also FIFO use is disabled
90 0 disables the FIFO use
91 if property is missing, then also FIFO use is disabled
/linux-6.15/drivers/scsi/aic7xxx/
H A Daic79xx.seq179 * the FIFO to complete the SCB.
308 * The FIFO use count field is shared with the
874 * Command retry. Free our current FIFO and
875 * re-allocate a FIFO so transfer state is
1234 * SCB is not transferring in the other FIFO.
1484 * any FIFO, it is important that we service a FIFO
1494 * this FIFO.
1499 * Switch to the other FIFO. Non-RTI chips
1512 * FIFO not currently on the bus first.
1543 * request in the other FIFO.
[all …]
/linux-6.15/arch/sparc/include/asm/
H A Dfloppy_64.h450 #define FIFO (port + 5) macro
469 sun_pci_fd_out_byte(port, 0x08, FIFO); in sun_pci_fd_sensei()
480 result[i++] = inb(FIFO); in sun_pci_fd_sensei()
515 sun_pci_fd_out_byte(port, 0x07, FIFO); in sun_pci_fd_test_drive()
516 sun_pci_fd_out_byte(port, drive & 0x03, FIFO); in sun_pci_fd_test_drive()
531 #undef FIFO
/linux-6.15/arch/powerpc/platforms/512x/
H A DKconfig14 tristate "MPC512x LocalPlus Bus FIFO driver"
17 Enable support for Freescale MPC512x LocalPlus Bus FIFO (SCLPC).
/linux-6.15/drivers/video/fbdev/nvidia/
H A Dnv_local.h92 NV_WR32(&(par)->FIFO[0x0010], 0, (data) << 2); \
96 #define READ_GET(par) (NV_RD32(&(par)->FIFO[0x0011], 0) >> 2)
/linux-6.15/Documentation/devicetree/bindings/memory-controllers/
H A Dqca,ath79-ddr-controller.yaml14 flush the FIFO between various devices and the DDR. This is mainly used by
15 the IRQ controller to flush the FIFO before running the interrupt handler of
/linux-6.15/sound/soc/cirrus/
H A DKconfig24 Underflow of internal I2S controller FIFO could confuse the
28 fills FIFO with zeroes.
/linux-6.15/Documentation/devicetree/bindings/spi/
H A Darm,pl022-peripheral-props.yaml33 description: Rx FIFO watermark level
39 description: Tx FIFO watermark level

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