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Searched refs:FIELD_PREP (Results 1 – 25 of 1120) sorted by relevance

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/linux-6.15/drivers/accel/habanalabs/include/gaudi/
H A Dgaudi_masks.h15 (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
16 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0xF)) | \
17 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0xF)))
20 (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \
21 (FIELD_PREP(DMA0_QM_GLBL_PROT_CQF_MASK, 0xF)) | \
22 (FIELD_PREP(DMA0_QM_GLBL_PROT_CP_MASK, 0xF)) | \
23 (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))
26 (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \
27 (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))
53 (FIELD_PREP(DMA0_QM_CGM_CFG_EN_MASK, 0x1)))
[all …]
/linux-6.15/drivers/iio/adc/
H A Dstm32-dfsdm.h115 #define DFSDM_CR1_DFEN(v) FIELD_PREP(DFSDM_CR1_DFEN_MASK, v)
137 #define DFSDM_CR1_RCH(v) FIELD_PREP(DFSDM_CR1_RCH_MASK, v)
139 #define DFSDM_CR1_FAST(v) FIELD_PREP(DFSDM_CR1_FAST_MASK, v)
145 #define DFSDM_CR2_IE(v) FIELD_PREP(DFSDM_CR2_IE_MASK, v)
161 #define DFSDM_CR2_EXCH(v) FIELD_PREP(DFSDM_CR2_EXCH_MASK, v)
175 #define DFSDM_ISR_AWDF(v) FIELD_PREP(DFSDM_ISR_AWDF_MASK, v)
177 #define DFSDM_ISR_JCIP(v) FIELD_PREP(DFSDM_ISR_JCIP_MASK, v)
179 #define DFSDM_ISR_RCIP(v) FIELD_PREP(DFSDM_ISR_RCIP, v)
183 #define DFSDM_ISR_SCDF(v) FIELD_PREP(DFSDM_ISR_SCDF_MASK, v)
203 #define DFSDM_FCR_IOSR(v) FIELD_PREP(DFSDM_FCR_IOSR_MASK, v)
[all …]
/linux-6.15/drivers/phy/microchip/
H A Dsparx5_serdes_regs.h57 FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)
74 FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_ADV, x)
80 FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_MAIN, x)
86 FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY, x)
1041 FIELD_PREP(SD10G_LANE_LANE_DF_LOL, x)
2301 FIELD_PREP(SD6G_LANE_LANE_DF_LOL, x)
2379 FIELD_PREP(SD_CMU_CMU_06_CFG_DCLOL, x)
2465 FIELD_PREP(SD_CMU_CMU_09_CFG_SW_8G, x)
2591 FIELD_PREP(SD_CMU_CMU_45_RESERVED, x)
2778 FIELD_PREP(SD_LANE_MISC_RX_ENA, x)
[all …]
H A Dlan966x_serdes_regs.h22 FIELD_PREP(HSIO_SD_CFG_PHY_RESET, x)
28 FIELD_PREP(HSIO_SD_CFG_TX_RESET, x)
34 FIELD_PREP(HSIO_SD_CFG_TX_RATE, x)
40 FIELD_PREP(HSIO_SD_CFG_TX_INVERT, x)
46 FIELD_PREP(HSIO_SD_CFG_TX_EN, x)
52 FIELD_PREP(HSIO_SD_CFG_TX_DATA_EN, x)
58 FIELD_PREP(HSIO_SD_CFG_TX_CM_EN, x)
76 FIELD_PREP(HSIO_SD_CFG_RX_RESET, x)
82 FIELD_PREP(HSIO_SD_CFG_RX_RATE, x)
88 FIELD_PREP(HSIO_SD_CFG_RX_PLL_EN, x)
[all …]
/linux-6.15/drivers/crypto/inside-secure/eip93/
H A Deip93-regs.h225 #define EIP93_SA_CMD_HASH_NULL FIELD_PREP(EIP93_SA_CMD_HASH, 0xf)
226 #define EIP93_SA_CMD_HASH_SHA256 FIELD_PREP(EIP93_SA_CMD_HASH, 0x3)
227 #define EIP93_SA_CMD_HASH_SHA224 FIELD_PREP(EIP93_SA_CMD_HASH, 0x2)
228 #define EIP93_SA_CMD_HASH_SHA1 FIELD_PREP(EIP93_SA_CMD_HASH, 0x1)
229 #define EIP93_SA_CMD_HASH_MD5 FIELD_PREP(EIP93_SA_CMD_HASH, 0x0)
231 #define EIP93_SA_CMD_CIPHER_NULL FIELD_PREP(EIP93_SA_CMD_CIPHER, 0xf)
232 #define EIP93_SA_CMD_CIPHER_AES FIELD_PREP(EIP93_SA_CMD_CIPHER, 0x3)
233 #define EIP93_SA_CMD_CIPHER_ARC4 FIELD_PREP(EIP93_SA_CMD_CIPHER, 0x2)
235 #define EIP93_SA_CMD_CIPHER_DES FIELD_PREP(EIP93_SA_CMD_CIPHER, 0x0)
244 #define EIP93_SA_CMD_OP_EXT FIELD_PREP(EIP93_SA_CMD_OPGROUP, 0x2)
[all …]
/linux-6.15/drivers/tty/serial/
H A Datmel_serial.h58 #define ATMEL_US_CHRL_5 FIELD_PREP(ATMEL_US_CHRL, 0)
59 #define ATMEL_US_CHRL_6 FIELD_PREP(ATMEL_US_CHRL, 1)
60 #define ATMEL_US_CHRL_7 FIELD_PREP(ATMEL_US_CHRL, 2)
61 #define ATMEL_US_CHRL_8 FIELD_PREP(ATMEL_US_CHRL, 3)
64 #define ATMEL_US_PAR_EVEN FIELD_PREP(ATMEL_US_PAR, 0)
65 #define ATMEL_US_PAR_ODD FIELD_PREP(ATMEL_US_PAR, 1)
66 #define ATMEL_US_PAR_SPACE FIELD_PREP(ATMEL_US_PAR, 2)
67 #define ATMEL_US_PAR_MARK FIELD_PREP(ATMEL_US_PAR, 3)
68 #define ATMEL_US_PAR_NONE FIELD_PREP(ATMEL_US_PAR, 4)
71 #define ATMEL_US_NBSTOP_1 FIELD_PREP(ATMEL_US_NBSTOP, 0)
[all …]
/linux-6.15/drivers/net/ethernet/microchip/lan966x/
H A Dlan966x_regs.h63 FIELD_PREP(ANA_ADVLEARN_VLAN_CHK, x)
75 FIELD_PREP(ANA_ANAINTR_INTR, x)
81 FIELD_PREP(ANA_ANAINTR_INTR_ENA, x)
90 FIELD_PREP(ANA_AUTOAGE_AGE_PERIOD, x)
165 FIELD_PREP(ANA_PGID_PGID, x)
201 FIELD_PREP(ANA_MACACCESS_VALID, x)
228 FIELD_PREP(ANA_MACTINDX_BUCKET, x)
369 FIELD_PREP(ANA_VCAP_CFG_S1_ENA, x)
1068 FIELD_PREP(PTP_DOM_CFG_ENA, x)
1240 FIELD_PREP(QS_INJ_CTRL_EOF, x)
[all …]
/linux-6.15/drivers/infiniband/hw/irdma/
H A Duda.c31 qw1 = FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_PDINDEXLO, info->pd_idx) | in irdma_sc_access_ah()
32 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_TC, info->tc_tos) | in irdma_sc_access_ah()
33 FIELD_PREP(IRDMA_UDAQPC_VLANTAG, info->vlan_tag); in irdma_sc_access_ah()
37 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_HOPLIMIT, info->hop_ttl) | in irdma_sc_access_ah()
69 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_WQEVALID, cqp->polarity) | in irdma_sc_access_ah()
70 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_OPCODE, op) | in irdma_sc_access_ah()
71 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_DOLOOPBACKK, info->do_lpbk) | in irdma_sc_access_ah()
72 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_IPV4VALID, info->ipv4_valid) | in irdma_sc_access_ah()
73 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_AVIDX, info->ah_idx) | in irdma_sc_access_ah()
158 FIELD_PREP(IRDMA_UDA_CQPSQ_MG_OPCODE, op) | in irdma_access_mcast_grp()
[all …]
H A Dctrl.c352 FIELD_PREP(IRDMA_CQPSQ_QHASH_OPCODE, in irdma_sc_manage_qhash_table_entry()
678 FIELD_PREP(IRDMAQPC_TTL, udp->ttl) | FIELD_PREP(IRDMAQPC_TOS, udp->tos) | in irdma_sc_qp_setctx_roce()
771 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, in irdma_sc_alloc_local_mac_entry()
809 FIELD_PREP(IRDMA_CQPSQ_OPCODE, in irdma_sc_add_local_mac_entry()
844 FIELD_PREP(IRDMA_CQPSQ_OPCODE, in irdma_sc_del_local_mac_entry()
932 FIELD_PREP(IRDMAQPC_RTOMIN, iw->rtomin); in irdma_sc_qp_setctx()
2248 FIELD_PREP(IRDMA_CQPSQ_FWQE_RQMJERR, in irdma_sc_qp_flush_wqes()
2253 FIELD_PREP(IRDMA_CQPSQ_FWQE_SQMJERR, in irdma_sc_qp_flush_wqes()
3171 FIELD_PREP(IRDMA_CQPHC_PROTOCOL_USED, in irdma_sc_cqp_create()
3476 FIELD_PREP(IRDMA_CQPSQ_OPCODE, in irdma_sc_manage_hmc_pm_func_table()
[all …]
H A Duk.c20 FIELD_PREP(IRDMAQPSQ_FRAG_TO, sge->addr)); in irdma_set_fragment()
22 FIELD_PREP(IRDMAQPSQ_VALID, valid) | in irdma_set_fragment()
23 FIELD_PREP(IRDMAQPSQ_FRAG_LEN, sge->length) | in irdma_set_fragment()
24 FIELD_PREP(IRDMAQPSQ_FRAG_STAG, sge->lkey)); in irdma_set_fragment()
28 FIELD_PREP(IRDMAQPSQ_VALID, valid)); in irdma_set_fragment()
44 FIELD_PREP(IRDMAQPSQ_FRAG_TO, sge->addr)); in irdma_set_fragment_gen_1()
78 FIELD_PREP(IRDMAQPSQ_SIGCOMPL, signaled) | in irdma_nop_1()
384 FIELD_PREP(IRDMAQPSQ_OPCODE, in irdma_uk_rdma_read()
474 FIELD_PREP(IRDMAQPSQ_IMMDATAFLAG, in irdma_uk_send()
692 FIELD_PREP(IRDMAQPSQ_INLINEDATAFLAG, 1) | in irdma_uk_inline_rdma_write()
[all …]
/linux-6.15/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_main_regs.h83 FIELD_PREP(ANA_AC_RAM_INIT_RAM_INIT, x)
4751 FIELD_PREP(FDMA_CH_CFG_CH_MEM, x)
4950 FIELD_PREP(FDMA_CTRL_NRESET, x)
4961 FIELD_PREP(GCB_CHIP_ID_REV_ID, x)
4967 FIELD_PREP(GCB_CHIP_ID_PART_ID, x)
4973 FIELD_PREP(GCB_CHIP_ID_MFG_ID, x)
4979 FIELD_PREP(GCB_CHIP_ID_ONE, x)
7055 FIELD_PREP(QS_XTR_FLUSH_FLUSH, x)
7101 FIELD_PREP(QS_INJ_CTRL_ABORT, x)
7107 FIELD_PREP(QS_INJ_CTRL_EOF, x)
[all …]
/linux-6.15/drivers/net/wireless/ath/ath11k/
H A Dhal_tx.c43 FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, ti->paddr); in ath11k_hal_tx_cmd_desc_setup()
45 FIELD_PREP(BUFFER_ADDR_INFO1_ADDR, in ath11k_hal_tx_cmd_desc_setup()
54 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ENCRYPT_TYPE, in ath11k_hal_tx_cmd_desc_setup()
56 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_SEARCH_TYPE, in ath11k_hal_tx_cmd_desc_setup()
58 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ADDR_EN, in ath11k_hal_tx_cmd_desc_setup()
60 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_CMD_NUM, in ath11k_hal_tx_cmd_desc_setup()
108 FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP1, in ath11k_hal_tx_set_dscp_tid_map()
110 FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP2, in ath11k_hal_tx_set_dscp_tid_map()
112 FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP3, in ath11k_hal_tx_set_dscp_tid_map()
114 FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP4, in ath11k_hal_tx_set_dscp_tid_map()
[all …]
H A Dhal_rx.c30 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc)); in ath11k_hal_reo_cmd_queue_stats()
62 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc)); in ath11k_hal_reo_cmd_flush_cache()
100 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc)); in ath11k_hal_reo_cmd_update_rx_queue()
123 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_AC, in ath11k_hal_reo_cmd_update_rx_queue()
155 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN, in ath11k_hal_reo_cmd_update_rx_queue()
161 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_VLD, in ath11k_hal_reo_cmd_update_rx_queue()
169 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_AC, in ath11k_hal_reo_cmd_update_rx_queue()
171 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_BAR, in ath11k_hal_reo_cmd_update_rx_queue()
175 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_RETRY, in ath11k_hal_reo_cmd_update_rx_queue()
207 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_SVLD, in ath11k_hal_reo_cmd_update_rx_queue()
[all …]
/linux-6.15/drivers/net/ethernet/meta/fbnic/
H A Dfbnic_mac.c22 FIELD_PREP(FBNIC_QM_TNI_TDF_CTL_CLS, cls); in fbnic_init_readrq()
105 FIELD_PREP(FBNIC_QM_TQS_MTU_CTL1_BULK, in fbnic_mac_init_qm()
117 FIELD_PREP(FBNIC_QM_TCQ_CTL0_COAL_WAIT, in fbnic_mac_init_qm()
126 FIELD_PREP(FBNIC_QM_RCQ_CTL0_COAL_WAIT, in fbnic_mac_init_qm()
206 FIELD_PREP(FBNIC_RXB_PBUF_BASE_ADDR, in fbnic_mac_init_rxb()
224 FIELD_PREP(FBNIC_RXB_PAUSE_THLD_ON, in fbnic_mac_init_rxb()
231 FIELD_PREP(FBNIC_RXB_DROP_THLD_ON, in fbnic_mac_init_rxb()
234 FIELD_PREP(FBNIC_RXB_DROP_THLD_OFF, in fbnic_mac_init_rxb()
243 FIELD_PREP(FBNIC_RXB_ECN_THLD_ON, in fbnic_mac_init_rxb()
247 FIELD_PREP(FBNIC_RXB_ECN_THLD_OFF, in fbnic_mac_init_rxb()
[all …]
/linux-6.15/drivers/phy/amlogic/
H A Dphy-meson-g12a-usb2.c193 FIELD_PREP(PHY_CTRL_R16_MPLL_M, 20) | in phy_meson_g12a_usb2_init()
194 FIELD_PREP(PHY_CTRL_R16_MPLL_N, 1) | in phy_meson_g12a_usb2_init()
209 FIELD_PREP(PHY_CTRL_R18_MPLL_LK_W, 9) | in phy_meson_g12a_usb2_init()
210 FIELD_PREP(PHY_CTRL_R18_MPLL_LK_S, 0x27) | in phy_meson_g12a_usb2_init()
211 FIELD_PREP(PHY_CTRL_R18_MPLL_PFD_GAIN, 1) | in phy_meson_g12a_usb2_init()
212 FIELD_PREP(PHY_CTRL_R18_MPLL_ROU, 7) | in phy_meson_g12a_usb2_init()
215 FIELD_PREP(PHY_CTRL_R18_MPLL_BB_MODE, 0) | in phy_meson_g12a_usb2_init()
216 FIELD_PREP(PHY_CTRL_R18_MPLL_ALPHA, 3) | in phy_meson_g12a_usb2_init()
217 FIELD_PREP(PHY_CTRL_R18_MPLL_ADJ_LDO, 1) | in phy_meson_g12a_usb2_init()
229 FIELD_PREP(PHY_CTRL_R16_MPLL_M, 20) | in phy_meson_g12a_usb2_init()
[all …]
/linux-6.15/drivers/crypto/ccree/
H A Dcc_hw_queue_defs.h245 FIELD_PREP(WORD1_DIN_SIZE, size) | in set_din_type()
246 FIELD_PREP(WORD1_NS_BIT, axi_sec); in set_din_type()
292 FIELD_PREP(WORD1_DIN_DMA_MODE, DMA_SRAM); in set_din_sram()
306 FIELD_PREP(WORD1_DIN_DMA_MODE, DMA_SRAM) | in set_din_const()
307 FIELD_PREP(WORD1_DIN_SIZE, size); in set_din_const()
338 FIELD_PREP(WORD3_DOUT_SIZE, size) | in set_dout_type()
339 FIELD_PREP(WORD3_NS_BIT, axi_sec); in set_dout_type()
450 FIELD_PREP(WORD3_DOUT_SIZE, size); in set_dout_sram()
548 pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_DO, in set_hw_crypto_key()
550 FIELD_PREP(WORD4_CIPHER_CONF2, in set_hw_crypto_key()
[all …]
/linux-6.15/drivers/phy/starfive/
H A Dphy-jh7110-dphy-tx.c217 writel(FIELD_PREP(STF_DPHY_RESETB, assert), in stf_dphy_hw_reset()
251 writel(FIELD_PREP(STF_DPHY_RG_CDTX_L0N_HSTX_RES, 0x10) | in stf_dphy_configure()
252 FIELD_PREP(STF_DPHY_RG_CDTX_L0P_HSTX_RES, 0x10), in stf_dphy_configure()
260 FIELD_PREP(STF_DPHY_RG_CDTX_L3P_HSTX_RES, 0x10), in stf_dphy_configure()
264 FIELD_PREP(STF_DPHY_RG_CDTX_L4P_HSTX_RES, 0x10), in stf_dphy_configure()
268 writel(FIELD_PREP(STF_DPHY_AON_POWER_READY_N, in stf_dphy_configure()
278 writel(FIELD_PREP(STF_DPHY_RG_CDTX_PLL_SSC_EN, 0x0), in stf_dphy_configure()
282 FIELD_PREP(STF_DPHY_RG_CDTX_PLL_FM_EN, 0x1) | in stf_dphy_configure()
283 FIELD_PREP(STF_DPHY_RG_CDTX_PLL_PRE_DIV, 0x0) | in stf_dphy_configure()
287 writel(FIELD_PREP(STF_DPHY_RG_CDTX_PLL_FBK_FRA, in stf_dphy_configure()
[all …]
/linux-6.15/drivers/phy/rockchip/
H A Dphy-rockchip-samsung-hdptx.c1318 FIELD_PREP(DIG_CLK_SEL_MASK, 0x1)); in rk_hdptx_dp_pll_init()
1338 FIELD_PREP(SB_AUX_EN_MASK, 0x1)); in rk_hdptx_dp_aux_init()
1381 FIELD_PREP(SB_AFC_TOL_MASK, 0x3)); in rk_hdptx_dp_aux_init()
1400 FIELD_PREP(OVRD_SB_EN_MASK, 0x1)); in rk_hdptx_dp_aux_init()
1422 FIELD_PREP(SB_EN_MASK, 0x1)); in rk_hdptx_dp_aux_init()
1428 FIELD_PREP(SB_VREG_EN_MASK, 0x1)); in rk_hdptx_dp_aux_init()
1431 FIELD_PREP(SB_AUX_EN_MASK, 0x1)); in rk_hdptx_dp_aux_init()
1574 FIELD_PREP(LCPLL_EN_MASK, 0x0)); in rk_hdptx_phy_set_rate()
1578 FIELD_PREP(ROPLL_EN_MASK, 0x1)); in rk_hdptx_phy_set_rate()
1592 FIELD_PREP(SSC_EN_MASK, 0x2)); in rk_hdptx_phy_set_rate()
[all …]
/linux-6.15/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-mediatek.c367 rmii_delay_val |= FIELD_PREP(MT8195_DLY_RMII_TXC_ENABLE, in mt8195_set_delay()
369 rmii_delay_val |= FIELD_PREP(MT8195_DLY_RMII_TXC_STAGES, in mt8195_set_delay()
371 rmii_delay_val |= FIELD_PREP(MT8195_DLY_RMII_TXC_INV, in mt8195_set_delay()
374 rmii_delay_val |= FIELD_PREP(MT8195_DLY_RMII_RXC_ENABLE, in mt8195_set_delay()
378 rmii_delay_val |= FIELD_PREP(MT8195_DLY_RMII_RXC_INV, in mt8195_set_delay()
392 delay_val |= FIELD_PREP(MT8195_DLY_RXC_ENABLE, in mt8195_set_delay()
394 delay_val |= FIELD_PREP(MT8195_DLY_RXC_STAGES, in mt8195_set_delay()
396 delay_val |= FIELD_PREP(MT8195_DLY_RXC_INV, in mt8195_set_delay()
403 delay_val |= FIELD_PREP(MT8195_DLY_TXC_ENABLE, in mt8195_set_delay()
405 delay_val |= FIELD_PREP(MT8195_DLY_TXC_STAGES, in mt8195_set_delay()
[all …]
/linux-6.15/drivers/i3c/master/mipi-i3c-hci/
H A Dcmd_v1.c23 #define CMD_0_ATTR_A FIELD_PREP(CMD_0_ATTR, 0x2)
29 #define CMD_A0_CMD(v) FIELD_PREP(W0_MASK(14, 7), v)
30 #define CMD_A0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v)
36 #define CMD_0_ATTR_I FIELD_PREP(CMD_0_ATTR, 0x1)
46 #define CMD_I0_MODE(v) FIELD_PREP(W0_MASK(28, 26), v)
47 #define CMD_I0_DTT(v) FIELD_PREP(W0_MASK(25, 23), v)
50 #define CMD_I0_CMD(v) FIELD_PREP(W0_MASK(14, 7), v)
51 #define CMD_I0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v)
57 #define CMD_0_ATTR_R FIELD_PREP(CMD_0_ATTR, 0x0)
75 #define CMD_0_ATTR_C FIELD_PREP(CMD_0_ATTR, 0x3)
[all …]
/linux-6.15/drivers/gpu/drm/xe/
H A Dxe_guc_hxg_helpers.h73 msg[0] = FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) | in guc_hxg_msg_encode_success()
74 FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_RESPONSE_SUCCESS) | in guc_hxg_msg_encode_success()
75 FIELD_PREP(GUC_HXG_RESPONSE_MSG_0_DATA0, data0); in guc_hxg_msg_encode_success()
82 msg[0] = FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) | in guc_hxg_msg_encode_failure()
83 FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_RESPONSE_FAILURE) | in guc_hxg_msg_encode_failure()
84 FIELD_PREP(GUC_HXG_FAILURE_MSG_0_HINT, hint) | in guc_hxg_msg_encode_failure()
85 FIELD_PREP(GUC_HXG_FAILURE_MSG_0_ERROR, error); in guc_hxg_msg_encode_failure()
92 msg[0] = FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) | in guc_hxg_msg_encode_busy()
94 FIELD_PREP(GUC_HXG_BUSY_MSG_0_COUNTER, counter); in guc_hxg_msg_encode_busy()
101 msg[0] = FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) | in guc_hxg_msg_encode_retry()
[all …]
/linux-6.15/drivers/firmware/samsung/
H A Dexynos-acpm-pmic.c59 FIELD_PREP(ACPM_PMIC_REG, reg) | in acpm_pmic_init_read_cmd()
60 FIELD_PREP(ACPM_PMIC_CHANNEL, chan); in acpm_pmic_init_read_cmd()
89 FIELD_PREP(ACPM_PMIC_REG, reg) | in acpm_pmic_init_bulk_read_cmd()
90 FIELD_PREP(ACPM_PMIC_CHANNEL, chan); in acpm_pmic_init_bulk_read_cmd()
92 FIELD_PREP(ACPM_PMIC_VALUE, count); in acpm_pmic_init_bulk_read_cmd()
131 FIELD_PREP(ACPM_PMIC_REG, reg) | in acpm_pmic_init_write_cmd()
134 FIELD_PREP(ACPM_PMIC_VALUE, value); in acpm_pmic_init_write_cmd()
162 FIELD_PREP(ACPM_PMIC_REG, reg) | in acpm_pmic_init_bulk_write_cmd()
165 FIELD_PREP(ACPM_PMIC_VALUE, count); in acpm_pmic_init_bulk_write_cmd()
200 FIELD_PREP(ACPM_PMIC_REG, reg) | in acpm_pmic_init_update_cmd()
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/linux-6.15/drivers/gpu/drm/meson/
H A Dmeson_overlay.c37 #define CANVAS_ADDR2(addr) FIELD_PREP(GENMASK(23, 16), addr)
38 #define CANVAS_ADDR1(addr) FIELD_PREP(GENMASK(15, 8), addr)
39 #define CANVAS_ADDR0(addr) FIELD_PREP(GENMASK(7, 0), addr)
42 #define VD_X_START(value) FIELD_PREP(GENMASK(14, 0), value)
43 #define VD_X_END(value) FIELD_PREP(GENMASK(30, 16), value)
46 #define VD_Y_START(value) FIELD_PREP(GENMASK(12, 0), value)
47 #define VD_Y_END(value) FIELD_PREP(GENMASK(28, 16), value)
61 #define VD_H_END(value) FIELD_PREP(GENMASK(11, 0), value)
62 #define VD_H_START(value) FIELD_PREP(GENMASK(27, 16), \
66 #define VD_V_END(value) FIELD_PREP(GENMASK(11, 0), value)
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/linux-6.15/drivers/pci/controller/dwc/
H A Dpcie-qcom-common.c25 reg |= FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, in qcom_pcie_common_set_16gt_equalization()
34 reg |= FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) | in qcom_pcie_common_set_16gt_equalization()
35 FIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) | in qcom_pcie_common_set_16gt_equalization()
36 FIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA, 0x5) | in qcom_pcie_common_set_16gt_equalization()
37 FIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA, 0x5); in qcom_pcie_common_set_16gt_equalization()
58 reg |= FIELD_PREP(MARGINING_MAX_VOLTAGE_OFFSET, 0x24) | in qcom_pcie_common_set_16gt_lane_margining()
59 FIELD_PREP(MARGINING_NUM_VOLTAGE_STEPS, 0x78) | in qcom_pcie_common_set_16gt_lane_margining()
60 FIELD_PREP(MARGINING_MAX_TIMING_OFFSET, 0x32) | in qcom_pcie_common_set_16gt_lane_margining()
61 FIELD_PREP(MARGINING_NUM_TIMING_STEPS, 0x10); in qcom_pcie_common_set_16gt_lane_margining()
74 FIELD_PREP(MARGINING_SAMPLE_RATE_TIMING, 0x3f) | in qcom_pcie_common_set_16gt_lane_margining()
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/linux-6.15/drivers/net/wireless/mediatek/mt76/mt76x2/
H A Dusb_phy.c64 [0] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 0) | in mt76x2u_phy_set_channel()
65 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 1) | in mt76x2u_phy_set_channel()
66 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) | in mt76x2u_phy_set_channel()
67 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) | in mt76x2u_phy_set_channel()
69 [1] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 1) | in mt76x2u_phy_set_channel()
70 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 0) | in mt76x2u_phy_set_channel()
71 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) | in mt76x2u_phy_set_channel()
72 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) | in mt76x2u_phy_set_channel()
74 [2] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 2) | in mt76x2u_phy_set_channel()
75 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 3) | in mt76x2u_phy_set_channel()
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