Searched refs:FCLK_DDR_CM0_CORE (Results 1 – 5 of 5) sorted by relevance
| /linux-6.15/include/dt-bindings/clock/ |
| H A D | rockchip,rk3576-cru.h | 239 #define FCLK_DDR_CM0_CORE 221 macro
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| H A D | rockchip,rk3588-cru.h | 227 #define FCLK_DDR_CM0_CORE 212 macro
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| /linux-6.15/drivers/clk/rockchip/ |
| H A D | clk-rk3576.c | 888 GATE(FCLK_DDR_CM0_CORE, "fclk_ddr_cm0_core", "hclk_ddr_root", CLK_IS_CRITICAL,
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| H A D | clk-rk3588.c | 1329 GATE(FCLK_DDR_CM0_CORE, "fclk_ddr_cm0_core", "hclk_center_root", CLK_IS_CRITICAL,
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| /linux-6.15/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3576.dtsi | 662 <&cru CLK_CPLL_DIV10>, <&cru FCLK_DDR_CM0_CORE>,
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