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Searched refs:ETH1_50MHZ_CLK (Results 1 – 2 of 2) sorted by relevance

/linux-6.15/include/dt-bindings/clock/
H A Dqcom,ipq-cmn-pll.h19 #define ETH1_50MHZ_CLK 7 macro
/linux-6.15/drivers/clk/qcom/
H A Dipq-cmn-pll.c115 CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL),