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Searched refs:EMC_SEL_DPD_CTRL (Results 1 – 5 of 5) sorted by relevance

/linux-6.15/drivers/memory/tegra/
H A Dtegra124-emc.c200 #define EMC_SEL_DPD_CTRL 0x3d8 macro
634 val = readl(emc->regs + EMC_SEL_DPD_CTRL); in tegra_emc_prepare_timing_change()
637 writel(val, emc->regs + EMC_SEL_DPD_CTRL); in tegra_emc_prepare_timing_change()
872 writel(timing->emc_sel_dpd_ctrl, emc->regs + EMC_SEL_DPD_CTRL); in tegra_emc_complete_timing_change()
H A Dtegra210-emc-cc-r21021.c473 emc_writel(emc, emc_sel_dpd_ctrl, EMC_SEL_DPD_CTRL); in tegra210_emc_r21021_set_clock()
496 emc_writel(emc, emc_sel_dpd_ctrl, EMC_SEL_DPD_CTRL); in tegra210_emc_r21021_set_clock()
1455 emc_writel(emc, next->emc_sel_dpd_ctrl, EMC_SEL_DPD_CTRL); in tegra210_emc_r21021_set_clock()
H A Dtegra210-emc.h187 #define EMC_SEL_DPD_CTRL 0x3d8 macro
H A Dtegra30-emc.c146 #define EMC_SEL_DPD_CTRL 0x3d8 macro
666 val = readl_relaxed(emc->regs + EMC_SEL_DPD_CTRL); in emc_prepare_timing_change()
/linux-6.15/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra124-emc.yaml144 value of the EMC_SEL_DPD_CTRL register for this set of timings