Home
last modified time | relevance | path

Searched refs:DSPP_0 (Results 1 – 25 of 35) sorted by relevance

12

/linux-6.15/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_6_3_sm6115.h64 .dspp = DSPP_0,
70 .name = "dspp_0", .id = DSPP_0,
H A Ddpu_6_5_qcm2290.h64 .dspp = DSPP_0,
70 .name = "dspp_0", .id = DSPP_0,
H A Ddpu_6_9_sm6375.h66 .dspp = DSPP_0,
72 .name = "dspp_0", .id = DSPP_0,
H A Ddpu_4_1_sdm670.h76 .dspp = DSPP_0,
104 .name = "dspp_0", .id = DSPP_0,
H A Ddpu_1_15_msm8917.h88 .dspp = DSPP_0,
105 .name = "dspp_0", .id = DSPP_0,
H A Ddpu_1_14_msm8937.h89 .dspp = DSPP_0,
119 .name = "dspp_0", .id = DSPP_0,
H A Ddpu_1_16_msm8953.h89 .dspp = DSPP_0,
119 .name = "dspp_0", .id = DSPP_0,
H A Ddpu_5_4_sm6125.h103 .dspp = DSPP_0,
118 .name = "dspp_0", .id = DSPP_0,
H A Ddpu_6_2_sc7180.h94 .dspp = DSPP_0,
107 .name = "dspp_0", .id = DSPP_0,
H A Ddpu_3_3_sdm630.h104 .dspp = DSPP_0,
134 .name = "dspp_0", .id = DSPP_0,
H A Ddpu_6_4_sm6350.h102 .dspp = DSPP_0,
116 .name = "dspp_0", .id = DSPP_0,
H A Ddpu_7_2_sc7280.h98 .dspp = DSPP_0,
118 .name = "dspp_0", .id = DSPP_0,
H A Ddpu_5_3_sm6150.h119 .dspp = DSPP_0,
137 .name = "dspp_0", .id = DSPP_0,
H A Ddpu_3_2_sdm660.h114 .dspp = DSPP_0,
184 .name = "dspp_0", .id = DSPP_0,
H A Ddpu_3_0_msm8998.h143 .dspp = DSPP_0,
213 .name = "dspp_0", .id = DSPP_0,
H A Ddpu_5_2_sm7150.h123 .dspp = DSPP_0,
151 .name = "dspp_0", .id = DSPP_0,
H A Ddpu_1_7_msm8996.h154 .dspp = DSPP_0,
224 .name = "dspp_0", .id = DSPP_0,
H A Ddpu_4_0_sdm845.h141 .dspp = DSPP_0,
171 .name = "dspp_0", .id = DSPP_0,
H A Ddpu_5_0_sm8150.h151 .dspp = DSPP_0,
195 .name = "dspp_0", .id = DSPP_0,
H A Ddpu_6_0_sm8250.h149 .dspp = DSPP_0,
193 .name = "dspp_0", .id = DSPP_0,
H A Ddpu_9_0_sm8550.h147 .dspp = DSPP_0,
191 .name = "dspp_0", .id = DSPP_0,
/linux-6.15/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_ctl.c156 for (dspp = DSPP_0; dspp < DSPP_MAX; dspp++) { in dpu_hw_ctl_trigger_flush_v1()
157 if (ctx->pending_dspp_flush_mask[dspp - DSPP_0]) in dpu_hw_ctl_trigger_flush_v1()
159 CTL_DSPP_n_FLUSH(dspp - DSPP_0), in dpu_hw_ctl_trigger_flush_v1()
160 ctx->pending_dspp_flush_mask[dspp - DSPP_0]); in dpu_hw_ctl_trigger_flush_v1()
365 case DSPP_0: in dpu_hw_ctl_update_pending_flush_dspp()
390 ctx->pending_dspp_flush_mask[dspp - DSPP_0] |= BIT(4); in dpu_hw_ctl_update_pending_flush_dspp_sub_blocks()
H A Ddpu_rm.h35 struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
H A Ddpu_kms.h130 uint32_t dspp_to_crtc_id[DSPP_MAX - DSPP_0];
H A Ddpu_hw_ctl.h292 u32 pending_dspp_flush_mask[DSPP_MAX - DSPP_0];

12